diff options
Diffstat (limited to 'roms/u-boot/board/davinci/da8xxevm')
| -rw-r--r-- | roms/u-boot/board/davinci/da8xxevm/Kconfig | 51 | ||||
| -rw-r--r-- | roms/u-boot/board/davinci/da8xxevm/MAINTAINERS | 14 | ||||
| -rw-r--r-- | roms/u-boot/board/davinci/da8xxevm/Makefile | 10 | ||||
| -rw-r--r-- | roms/u-boot/board/davinci/da8xxevm/README.da850 | 157 | ||||
| -rw-r--r-- | roms/u-boot/board/davinci/da8xxevm/da850evm.c | 466 | ||||
| -rw-r--r-- | roms/u-boot/board/davinci/da8xxevm/omapl138_lcdk.c | 392 | ||||
| -rw-r--r-- | roms/u-boot/board/davinci/da8xxevm/u-boot-spl-da850evm.lds | 65 |
7 files changed, 1155 insertions, 0 deletions
diff --git a/roms/u-boot/board/davinci/da8xxevm/Kconfig b/roms/u-boot/board/davinci/da8xxevm/Kconfig new file mode 100644 index 000000000..bb1188b4e --- /dev/null +++ b/roms/u-boot/board/davinci/da8xxevm/Kconfig @@ -0,0 +1,51 @@ +if TARGET_DA850EVM + +config SYS_BOARD + default "da8xxevm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "da850evm" + +menuconfig DA850_MAC + bool "Use MAC Address" + default y + +if DA850_MAC +config MAC_ADDR_IN_SPIFLASH + bool "MAC address in SPI Flash" + default y + help + The OMAP-L138 and AM1808 SoM are programmed with + their MAC address in SPI Flash from the factory + Enable this option to read the MAC from SPI Flash + +config MAC_ADDR_IN_EEPROM + bool "MAC address in EEPROM" + help + The DA850 EVM comes with SoM are programmed with + their MAC address in SPI Flash from the factory, + but the kit has an optional expansion board with + EEPROM available. Enable this option to read the + MAC from the EEPROM + +endif + +endif + +if TARGET_OMAPL138_LCDK + +config SYS_BOARD + default "da8xxevm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "omapl138_lcdk" + +endif + +source "board/ti/common/Kconfig" diff --git a/roms/u-boot/board/davinci/da8xxevm/MAINTAINERS b/roms/u-boot/board/davinci/da8xxevm/MAINTAINERS new file mode 100644 index 000000000..16f103266 --- /dev/null +++ b/roms/u-boot/board/davinci/da8xxevm/MAINTAINERS @@ -0,0 +1,14 @@ +DA850_EVM BOARD +M: Adam Ford <aford173@gmail.com> +S: Maintained +F: board/davinci/da8xxevm/ +F: include/configs/da850evm.h +F: configs/da850evm_defconfig +F: configs/da850evm_nand_defconfig +F: configs/da850evm_direct_nor_defconfig + +OMAPL138_LCDK BOARD +M: Lokesh Vutla <lokeshvutla@ti.com> +S: Maintained +F: include/configs/omap1l38_lcdk.h +F: configs/omapl138_lcdk_defconfig diff --git a/roms/u-boot/board/davinci/da8xxevm/Makefile b/roms/u-boot/board/davinci/da8xxevm/Makefile new file mode 100644 index 000000000..3fac615d7 --- /dev/null +++ b/roms/u-boot/board/davinci/da8xxevm/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + +obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o +obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o +obj-$(CONFIG_MACH_OMAPL138_LCDK) += omapl138_lcdk.o diff --git a/roms/u-boot/board/davinci/da8xxevm/README.da850 b/roms/u-boot/board/davinci/da8xxevm/README.da850 new file mode 100644 index 000000000..8cebdcc1b --- /dev/null +++ b/roms/u-boot/board/davinci/da8xxevm/README.da850 @@ -0,0 +1,157 @@ +Summary +======= +The README is for the boot procedure used for various DA850 (or compatible +parts such as the AM1808) based boards. + +In the context of U-Boot, the board is booted in three stages. The initial +bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits +in the internal ROM. The RBL initializes the internal memory and then +depending on the exact board and pin configurations will initialize another +controller (such as SPI or NAND) to continue the boot process by loading +the secondary program loader (SPL). The SPL will initialize the system +further (some clocks, SDRAM) and then load the full u-boot from a +predefined location in persistent storage to DDR and jumps to the u-boot +entry point. + +AIS is an image format defined by TI for the images that are to be loaded +to memory by the RBL. The image is divided into a series of sections and +the image's entry point is specified. Each section comes with meta data +like the target address the section is to be copied to and the size of the +section, which is used by the RBL to load the image. At the end of the +image the RBL jumps to the image entry point. The AIS format allows for +other things such as programming the clocks and SDRAM if the header is +programmed for it. We do not take advantage of this and instead use SPL as +it allows for additional flexibility (run-time detect of board revision, +loading the next image from a different media, etc). + + +Compilation +=========== +The exact build target you need will depend on the board you have. For +Logic PD boards, or other boards which store the ethernet MAC address at +the end of SPI flash, run 'make da850evm'. Once this build completes you will have a +u-boot.ais file that needs to be written to the correct persistent +storage. + + +Flashing the images to SPI +========================== +The AIS image can be written to SPI flash using the following commands. +Assuming that the network is configured and enabled and the u-boot.ais file +is tftp'able. + +U-Boot > sf probe 0 +U-Boot > sf erase 0 +320000 +U-Boot > tftp u-boot.ais +U-Boot > sf write c0700000 0 $filesize + +Flashing the images to NAND +=========================== +The AIS image can be written to NAND using the u-boot "nand" commands. + +Example: + +OMAPL138_LCDK requires the AIS image to be written to the second block of +the NAND flash. + +From the "nand info" command we see that the second block would start at +offset 0x20000: + + U-Boot > nand info + sector size 128 KiB (0x20000) + Page size 2048 b + +From the tftp command we see that we need to copy 0x74908 bytes from +memory address 0xc0700000 (0x75000 if we align a page of 2048): + + U-Boot > tftp u-boot.ais + Load address: 0xc0700000 + Bytes transferred = 477448 (74908 hex) + +The commands to write the image from memory to NAND would be: + + U-Boot > nand erase 0x20000 0x75000 + U-Boot > nand write 0xc0700000 0x20000 0x75000 + +Alternatively, MTD partitions may be defined. Using "mtdparts" to +conveniently have a bootloader partition starting at the second block +(offset 0x20000): + + setenv mtdids nand0=davinci_nand.0 + setenv mtdparts mtdparts=davinci_nand.0:128k(bootenv),2m(bootloader) + +In this case the commands would be simplified to: + + U-Boot > tftp u-boot.ais + U-Boot > nand erase.part bootloader + U-Boot > nand write 0xc0700000 bootloader + +On the DA850-EVM, NAND can also be written with SW7:7-8 ON and + + sudo mono sfh_OMAP-L138.exe -targetType AM1808 -p /dev/ttyUSB0 \ + -flash_noubl -flashType NAND ~/src/u-boot/u-boot.ais + +To boot the DA850-EVM from NAND, SW7:5 should be switched on and all others +off. + +Flashing the images to MMC +========================== +If the boot pins are set to boot from mmc, the RBL will try to load the +next boot stage form the first couple of sectors of an external mmc card. +As sector 0 is usually used for storing the partition information, the +AIS image should be written at least after the first sector, but before the +first partition begins. (e.g: make sure to leave at least 500KB of unallocated +space at the start of the mmc when creating the partitions) + +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is used by SPL, and should +point to the sector were the u-boot image is located. (eg. After SPL) + +There are 2 ways to copy the AIS image to the mmc card: + + 1 - Using the TI tool "uflash" + $ uflash -d /dev/mmcblk0 -b ./u-boot.ais -p OMAPL138 -vv + + 2 - using the "dd" command + $ dd if=u-boot.ais of=/dev/mmcblk0 seek=117 bs=512 conv=fsync + +uflash writes the AIS image at offset 117. For compatibility with uflash, +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is set to take into account this +offset, and the dd command is adjusted accordingly. + +Flashing the images to NOR +========================== +NOR Flash is XIP (execute-in-place), so no AIS (or SPL) is needed. The +u-boot.bin is directy flashed, but CONFIT_DA850_LOWLEVEL must be set +to initialize hardware that's normally done by SPL. + +For this case, CONFIG_SYS_TEXT_BASE=0x60000000 which is the address to +which the bootloader jumps when powered on. + +Example: +For the da850evm, there is a defconfig setup to use the NOR flash on +the UI expander board called da850evm_direct_nor_defconfig. + +Flash to NOR directly using +sudo mono ./sfh_OMAP-L138.exe -p /dev/ttyUSB0 -flash_noubl + -flashType NOR u-boot.bin + +SW7:5 through SW7:7 should be switched on and all others off. + +Recovery +======== + +In the case of a "bricked" board, you need to use the TI tools found +here[1] to write the u-boot.ais file. An example of recovering to the SPI +flash of an AM1808 would be: + +$ mono sfh_OMAP-L138.exe -targetType AM1808 -p /dev/ttyUSB0 \ + -flash_noubl /path/to/u-boot.ais + +For other target types and flash locations: + +$ mono sfh_OMAP-L138.exe -h + +Links +===== +[1] + http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138 diff --git a/roms/u-boot/board/davinci/da8xxevm/da850evm.c b/roms/u-boot/board/davinci/da8xxevm/da850evm.c new file mode 100644 index 000000000..383a86173 --- /dev/null +++ b/roms/u-boot/board/davinci/da8xxevm/da850evm.c @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <i2c.h> +#include <init.h> +#include <net.h> +#include <spi.h> +#include <spi_flash.h> +#include <asm/arch/hardware.h> +#include <asm/global_data.h> +#include <asm/ti-common/davinci_nand.h> +#include <asm/arch/emac_defs.h> +#include <asm/arch/pinmux_defs.h> +#include <asm/io.h> +#include <asm/arch/davinci_misc.h> +#include <linux/errno.h> +#include <hwconfig.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> + +#ifdef CONFIG_MMC_DAVINCI +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DRIVER_TI_EMAC +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII +#define HAS_RMII 1 +#else +#define HAS_RMII 0 +#endif +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#define CFG_MAC_ADDR_SPI_BUS 0 +#define CFG_MAC_ADDR_SPI_CS 0 +#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 + +#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) + +#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH +static int get_mac_addr(u8 *addr) +{ + struct spi_flash *flash; + int ret; + + flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS, + CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE); + if (!flash) { + printf("Error - unable to probe SPI flash.\n"); + return -1; + } + + ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr); + if (ret) { + printf("Error - unable to read MAC address from SPI flash.\n"); + return -1; + } + + return ret; +} +#endif + +void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + u32 val; + + /* if the device is ARM only, return */ + if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) *10); + + /* setup the DSP reset vector */ + writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + val = readl(PSC0_MDCTL + (15 * 4)); + val |= 0x100; + writel(val, (PSC0_MDCTL + (15 * 4))); +} + +int misc_init_r(void) +{ + dspwake(); + +#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM) + + uchar env_enetaddr[6]; + int enetaddr_found; + + enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr); + +#endif + +#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH + int spi_mac_read; + uchar buff[6]; + + spi_mac_read = get_mac_addr(buff); + buff[0] = 0; + + /* + * MAC address not present in the environment + * try and read the MAC address from SPI flash + * and set it. + */ + if (!enetaddr_found) { + if (!spi_mac_read) { + if (is_valid_ethaddr(buff)) { + if (eth_env_set_enetaddr("ethaddr", buff)) { + printf("Warning: Failed to " + "set MAC address from SPI flash\n"); + } + } else { + printf("Warning: Invalid " + "MAC address read from SPI flash\n"); + } + } + } else { + /* + * MAC address present in environment compare it with + * the MAC address in SPI flash and warn on mismatch + */ + if (!spi_mac_read && is_valid_ethaddr(buff) && + memcmp(env_enetaddr, buff, 6)) + printf("Warning: MAC address in SPI flash don't match " + "with the MAC address in the environment\n"); + printf("Default using MAC address from environment\n"); + } + +#elif defined(CONFIG_MAC_ADDR_IN_EEPROM) + uint8_t enetaddr[8]; + int eeprom_mac_read; + + /* Read Ethernet MAC address from EEPROM */ + eeprom_mac_read = dvevm_read_mac_address(enetaddr); + + /* + * MAC address not present in the environment + * try and read the MAC address from EEPROM flash + * and set it. + */ + if (!enetaddr_found) { + if (eeprom_mac_read) + /* Set Ethernet MAC address from EEPROM */ + davinci_sync_env_enetaddr(enetaddr); + } else { + /* + * MAC address present in environment compare it with + * the MAC address in EEPROM and warn on mismatch + */ + if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) + printf("Warning: MAC address in EEPROM don't match " + "with the MAC address in the environment\n"); + printf("Default using MAC address from environment\n"); + } + +#endif + return 0; +} + +static const struct pinmux_config gpio_pins[] = { +#ifdef CONFIG_MTD_NOR_FLASH + /* GP0[11] is required for NOR to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ +#endif +#ifdef CONFIG_MMC_DAVINCI + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ +#endif +}; + +const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_DRIVER_TI_EMAC + PINMUX_ITEM(emac_pins_mdio), +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + PINMUX_ITEM(emac_pins_rmii), +#else + PINMUX_ITEM(emac_pins_mii), +#endif +#endif +#ifdef CONFIG_SPI_FLASH + PINMUX_ITEM(spi1_pins_base), + PINMUX_ITEM(spi1_pins_scs0), +#endif + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(i2c0_pins), +#ifdef CONFIG_NAND_DAVINCI + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), +#elif defined(CONFIG_MTD_NOR_FLASH) + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_nor), +#endif + PINMUX_ITEM(gpio_pins), +#ifdef CONFIG_MMC_DAVINCI + PINMUX_ITEM(mmc0_pins), +#endif +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_GPIO }, +#ifdef CONFIG_MMC_DAVINCI + { DAVINCI_LPSC_MMC_SD }, +#endif +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + +#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK +#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 +#endif + +#define REV_AM18X_EVM 0x100 + +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] Maximum cpu clock rate supported by onboard SoC + * 0000b - 300 MHz + * 0001b - 372 MHz + * 0010b - 408 MHz + * 0011b - 456 MHz + */ +u32 get_board_rev(void) +{ + char *s; + u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; + u32 rev = 0; + + s = env_get("maxcpuclk"); + if (s) + maxcpuclk = simple_strtoul(s, NULL, 10); + + if (maxcpuclk >= 456000000) + rev = 3; + else if (maxcpuclk >= 408000000) + rev = 2; + else if (maxcpuclk >= 372000000) + rev = 1; + return rev; +} + +int board_early_init_f(void) +{ + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + return 0; +} + +int board_init(void) +{ + irq_init(); + +#ifdef CONFIG_NAND_DAVINCI + /* + * NAND CS setup - cycle counts based on da850evm NAND timings in the + * Linux kernel @ 25MHz EMIFA + */ + writel((DAVINCI_ABCR_WSETUP(2) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(1) | + DAVINCI_ABCR_RSETUP(1) | + DAVINCI_ABCR_RSTROBE(4) | + DAVINCI_ABCR_RHOLD(0) | + DAVINCI_ABCR_TA(1) | + DAVINCI_ABCR_ASIZE_8BIT), + &davinci_emif_regs->ab2cr); /* CS3 */ +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART2), + &davinci_syscfg_regs->suspsrc); + +#ifdef CONFIG_MTD_NOR_FLASH + /* Set the GPIO direction as output */ + clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + + /* Set the output as low */ + writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR); +#endif + +#ifdef CONFIG_MMC_DAVINCI + /* Set the GPIO direction as output */ + clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + + /* Set the output as high */ + writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR); +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC + davinci_emac_mii_mode_sel(HAS_RMII); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII +/** + * rmii_hw_init + * + * DA850/OMAP-L138 EVM can interface to a daughter card for + * additional features. This card has an I2C GPIO Expander TCA6416 + * to select the required functions like camera, RMII Ethernet, + * character LCD, video. + * + * Initialization of the expander involves configuring the + * polarity and direction of the ports. P07-P05 are used here. + * These ports are connected to a Mux chip which enables only one + * functionality at a time. + * + * For RMII phy to respond, the MII MDIO clock has to be disabled + * since both the PHY devices have address as zero. The MII MDIO + * clock is controlled via GPIO2[6]. + * + * This code is valid for Beta version of the hardware + */ +int rmii_hw_init(void) +{ + const struct pinmux_config gpio_pins[] = { + { pinmux(6), 8, 1 } + }; + u_int8_t buf[2]; + unsigned int temp; + int ret; + + /* PinMux for GPIO */ + if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) + return 1; + + /* I2C Exapnder configuration */ + /* Set polarity to non-inverted */ + buf[0] = 0x0; + buf[1] = 0x0; + ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); + if (ret) { + printf("\nExpander @ 0x%02x write FAILED!!!\n", + CONFIG_SYS_I2C_EXPANDER_ADDR); + return ret; + } + + /* Configure P07-P05 as outputs */ + buf[0] = 0x1f; + buf[1] = 0xff; + ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); + if (ret) { + printf("\nExpander @ 0x%02x write FAILED!!!\n", + CONFIG_SYS_I2C_EXPANDER_ADDR); + } + + /* For Ethernet RMII selection + * P07(SelA)=0 + * P06(SelB)=1 + * P05(SelC)=1 + */ + if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + printf("\nExpander @ 0x%02x read FAILED!!!\n", + CONFIG_SYS_I2C_EXPANDER_ADDR); + } + + buf[0] &= 0x1f; + buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); + if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + printf("\nExpander @ 0x%02x write FAILED!!!\n", + CONFIG_SYS_I2C_EXPANDER_ADDR); + } + + /* Set the output as high */ + temp = REG(GPIO_BANK2_REG_SET_ADDR); + temp |= (0x01 << 6); + REG(GPIO_BANK2_REG_SET_ADDR) = temp; + + /* Set the GPIO direction as output */ + temp = REG(GPIO_BANK2_REG_DIR_ADDR); + temp &= ~(0x01 << 6); + REG(GPIO_BANK2_REG_DIR_ADDR) = temp; + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ + +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + /* Select RMII fucntion through the expander */ + if (rmii_hw_init()) + printf("RMII hardware init failed!!!\n"); +#endif + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/roms/u-boot/board/davinci/da8xxevm/omapl138_lcdk.c b/roms/u-boot/board/davinci/da8xxevm/omapl138_lcdk.c new file mode 100644 index 000000000..d5f43bf52 --- /dev/null +++ b/roms/u-boot/board/davinci/da8xxevm/omapl138_lcdk.c @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da850evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + */ + +#include <common.h> +#include <env.h> +#include <i2c.h> +#include <init.h> +#include <net.h> +#include <asm/arch/hardware.h> +#include <asm/global_data.h> +#include <asm/ti-common/davinci_nand.h> +#include <asm/io.h> +#include <ns16550.h> +#include <dm/platdata.h> +#include <linux/errno.h> +#include <asm/mach-types.h> +#include <asm/arch/davinci_misc.h> +#ifdef CONFIG_MMC_DAVINCI +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) + +#ifdef CONFIG_MMC_DAVINCI +/* MMC0 pin muxer settings */ +const struct pinmux_config mmc0_pins[] = { + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ + { pinmux(10), 2, 0 }, /* MMCSD0_CLK */ + { pinmux(10), 2, 1 }, /* MMCSD0_CMD */ + { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */ + { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */ + { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */ + { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */ + /* LCDK supports only 4-bit mode, remaining pins are not configured */ +}; +#endif + +/* UART pin muxer settings */ +static const struct pinmux_config uart_pins[] = { + { pinmux(0), 4, 6 }, + { pinmux(0), 4, 7 }, + { pinmux(4), 2, 4 }, + { pinmux(4), 2, 5 } +}; + +#ifdef CONFIG_DRIVER_TI_EMAC +static const struct pinmux_config emac_pins[] = { + { pinmux(2), 8, 1 }, + { pinmux(2), 8, 2 }, + { pinmux(2), 8, 3 }, + { pinmux(2), 8, 4 }, + { pinmux(2), 8, 5 }, + { pinmux(2), 8, 6 }, + { pinmux(2), 8, 7 }, + { pinmux(3), 8, 0 }, + { pinmux(3), 8, 1 }, + { pinmux(3), 8, 2 }, + { pinmux(3), 8, 3 }, + { pinmux(3), 8, 4 }, + { pinmux(3), 8, 5 }, + { pinmux(3), 8, 6 }, + { pinmux(3), 8, 7 }, + { pinmux(4), 8, 0 }, + { pinmux(4), 8, 1 } +}; +#endif /* CONFIG_DRIVER_TI_EMAC */ + +/* I2C pin muxer settings */ +static const struct pinmux_config i2c_pins[] = { + { pinmux(4), 2, 2 }, + { pinmux(4), 2, 3 } +}; + +#ifdef CONFIG_NAND_DAVINCI +const struct pinmux_config nand_pins[] = { + { pinmux(7), 1, 1 }, + { pinmux(7), 1, 2 }, + { pinmux(7), 1, 4 }, + { pinmux(7), 1, 5 }, + { pinmux(8), 1, 0 }, + { pinmux(8), 1, 1 }, + { pinmux(8), 1, 2 }, + { pinmux(8), 1, 3 }, + { pinmux(8), 1, 4 }, + { pinmux(8), 1, 5 }, + { pinmux(8), 1, 6 }, + { pinmux(8), 1, 7 }, + { pinmux(9), 1, 0 }, + { pinmux(9), 1, 1 }, + { pinmux(9), 1, 2 }, + { pinmux(9), 1, 3 }, + { pinmux(9), 1, 4 }, + { pinmux(9), 1, 5 }, + { pinmux(9), 1, 6 }, + { pinmux(9), 1, 7 }, + { pinmux(12), 1, 5 }, + { pinmux(12), 1, 6 } +}; + +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII +#define HAS_RMII 1 +#else +#define HAS_RMII 0 +#endif + +const struct pinmux_resource pinmuxes[] = { + PINMUX_ITEM(uart_pins), + PINMUX_ITEM(i2c_pins), +#ifdef CONFIG_NAND_DAVINCI + PINMUX_ITEM(nand_pins), +#endif +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_GPIO }, +#ifdef CONFIG_MMC_DAVINCI + { DAVINCI_LPSC_MMC_SD }, +#endif +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + +#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK +#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000 +#endif + +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] Maximum cpu clock rate supported by onboard SoC + * 0000b - 300 MHz + * 0001b - 372 MHz + * 0010b - 408 MHz + * 0011b - 456 MHz + */ +u32 get_board_rev(void) +{ + return 0; +} + +int board_early_init_f(void) +{ + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + return 0; +} + +int board_init(void) +{ + irq_init(); + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART2), + &davinci_syscfg_regs->suspsrc); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) + return 1; + +#ifdef CONFIG_NAND_DAVINCI + /* + * NAND CS setup - cycle counts based on da850evm NAND timings in the + * Linux kernel @ 25MHz EMIFA + */ + writel((DAVINCI_ABCR_WSETUP(15) | + DAVINCI_ABCR_WSTROBE(63) | + DAVINCI_ABCR_WHOLD(7) | + DAVINCI_ABCR_RSETUP(15) | + DAVINCI_ABCR_RSTROBE(63) | + DAVINCI_ABCR_RHOLD(7) | + DAVINCI_ABCR_TA(3) | + DAVINCI_ABCR_ASIZE_16BIT), + &davinci_emif_regs->ab2cr); /* CS3 */ +#endif + + +#ifdef CONFIG_MMC_DAVINCI + if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0) + return 1; +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC + if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) + return 1; + davinci_emac_mii_mode_sel(HAS_RMII); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + /* enable the console UART */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart2_ctrl_regs->pwremu_mgmt); + + return 0; +} + +#define CFG_MAC_ADDR_SPI_BUS 0 +#define CFG_MAC_ADDR_SPI_CS 0 +#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 + +#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) + +static int get_mac_addr(u8 *addr) +{ + /* Need to find a way to get MAC ADDRESS */ + return 0; +} + +void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + + /* if the device is ARM only, return */ + if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (!strcmp(env_get("dspwake"), "no")) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) * 10); + + /* setup the DSP reset vector */ + REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE; + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + REG(PSC0_MDCTL + (15 * 4)) |= 0x100; +} + +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII +/** + * rmii_hw_init + * + */ +int rmii_hw_init(void) +{ + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ + +int misc_init_r(void) +{ + uint8_t tmp[20], addr[10]; + + + if (env_get("ethaddr") == NULL) { + /* Read Ethernet MAC address from EEPROM */ + if (dvevm_read_mac_address(addr)) { + /* Set Ethernet MAC address from EEPROM */ + davinci_sync_env_enetaddr(addr); + } else { + get_mac_addr(addr); + } + + if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) { + sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", + addr[0], addr[1], addr[2], addr[3], addr[4], + addr[5]); + + env_set("ethaddr", (char *)tmp); + } else { + printf("Invalid MAC address read.\n"); + } + } + +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + /* Select RMII fucntion through the expander */ + if (rmii_hw_init()) + printf("RMII hardware init failed!!!\n"); +#endif + + dspwake(); + + return 0; +} + +#if !CONFIG_IS_ENABLED(DM_MMC) +#ifdef CONFIG_MMC_DAVINCI +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +int board_mmc_init(struct bd_info *bis) +{ + mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); + + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd0); +} +#endif +#endif + +#ifdef CONFIG_SPL_BUILD +static const struct ns16550_plat serial_pdata = { + .base = DAVINCI_UART2_BASE, + .reg_shift = 2, + .clock = 228000000, + .fcr = UART_FCR_DEFVAL, +}; + +U_BOOT_DRVINFO(omapl138_uart) = { + .name = "ns16550_serial", + .plat = &serial_pdata, +}; + +static const struct davinci_mmc_plat mmc_plat = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .cfg = { + .f_min = 200000, + .f_max = 25000000, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .host_caps = MMC_MODE_4BIT, + .b_max = DAVINCI_MAX_BLOCKS, + .name = "da830-mmc", + }, +}; +U_BOOT_DRVINFO(omapl138_mmc) = { + .name = "ti_da830_mmc", + .plat = &mmc_plat, +}; + +void spl_board_init(void) +{ + davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)); +} +#endif diff --git a/roms/u-boot/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/roms/u-boot/board/davinci/da8xxevm/u-boot-spl-da850evm.lds new file mode 100644 index 000000000..8f0491130 --- /dev/null +++ b/roms/u-boot/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + */ + +MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_FOOTPRINT } + +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/arm926ejs/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram + + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } >.sram + + __image_copy_end = .; + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} |