diff options
Diffstat (limited to 'roms/u-boot/board/freescale/ls1012ardb')
| -rw-r--r-- | roms/u-boot/board/freescale/ls1012ardb/Kconfig | 124 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/ls1012ardb/MAINTAINERS | 18 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/ls1012ardb/Makefile | 8 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/ls1012ardb/README | 97 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/ls1012ardb/eth.c | 171 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/ls1012ardb/ls1012ardb.c | 426 |
6 files changed, 844 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/ls1012ardb/Kconfig b/roms/u-boot/board/freescale/ls1012ardb/Kconfig new file mode 100644 index 000000000..c4acea3ae --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012ardb/Kconfig @@ -0,0 +1,124 @@ +if TARGET_LS1012ARDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012ardb" + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 + +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA Firmware HDR Addr" + default 0x40680000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40640000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 +endif + +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHY_REALTEK + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + +source "board/freescale/common/Kconfig" + +endif + +if TARGET_LS1012A2G5RDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012a2g5rdb" + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 + +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHYLIB_10G + imply PHY_AQUANTIA + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + +source "board/freescale/common/Kconfig" + +endif diff --git a/roms/u-boot/board/freescale/ls1012ardb/MAINTAINERS b/roms/u-boot/board/freescale/ls1012ardb/MAINTAINERS new file mode 100644 index 000000000..b0c008b5f --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012ardb/MAINTAINERS @@ -0,0 +1,18 @@ +LS1012ARDB BOARD +M: Rajesh Bhagat <rajesh.bhagat@nxp.com> +M: Pramod Kumar <pramod.kumar_1@nxp.com> +S: Maintained +F: board/freescale/ls1012ardb/ +F: include/configs/ls1012ardb.h +F: configs/ls1012ardb_qspi_defconfig +F: configs/ls1012ardb_tfa_defconfig +F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +F: configs/ls1012a2g5rdb_tfa_defconfig +F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig + +LS1012A2G5RDB BOARD +M: Pramod Kumar <pramod.kumar_1@nxp.com> +S: Maintained +F: board/freescale/ls1012ardb/ +F: include/configs/ls1012a2g5rdb.h +F: configs/ls1012a2g5rdb_qspi_defconfig diff --git a/roms/u-boot/board/freescale/ls1012ardb/Makefile b/roms/u-boot/board/freescale/ls1012ardb/Makefile new file mode 100644 index 000000000..70c7b3327 --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012ardb/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012ardb.o +obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/roms/u-boot/board/freescale/ls1012ardb/README b/roms/u-boot/board/freescale/ls1012ardb/README new file mode 100644 index 000000000..572fd8c7d --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012ardb/README @@ -0,0 +1,97 @@ +Overview +-------- +QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance +development platform, with a complete debugging environment. +The LS1012ARDB board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + +LS1012ARDB board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory (2 virtual banks) + - the QSPI emulator.s + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: Three dual 1:4 mux/demux devices, + 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, + SDIO WiFi, SPI, and Ardiuno shield + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on RDB. + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 + +LS1012A2G5RDB board Overview +----------------------- + - SERDES Connections, 3 lanes supporting: + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - SDIO WiFi, SPI + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on 2G5RDB. + - ARM JTAG support + +Major Difference between LS1012ARDB and LS1012A-2G5RDB +------------------------------------------------------ +1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB +2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs + of LS1012ARDB +3. LS1012A-2G5RDB is not having Arduino header +4. LS1012A-2G5RDB doesn't have PCI slot + +Booting Options +--------------- +QSPI Flash + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4030_0000 +PPA FIT image | 2MB | 0x4040_0000 +PFE firmware | 20K | 0x00a0_0000 +Linux ITB | ~53MB | 0x4100_0000 diff --git a/roms/u-boot/board/freescale/ls1012ardb/eth.c b/roms/u-boot/board/freescale/ls1012ardb/eth.c new file mode 100644 index 000000000..bb3fbc71e --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012ardb/eth.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include <common.h> +#include <dm.h> +#include <net.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <asm/types.h> +#include <fsl_dtsec.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/config.h> +#include <asm/arch-fsl-layerscape/immap_lsch2.h> +#include <asm/arch/fsl_serdes.h> +#include <linux/delay.h> +#include <net/pfe_eth/pfe_eth.h> +#include <dm/platform_data/pfe_dm_eth.h> +#include <i2c.h> + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" + +static inline void ls1012ardb_reset_phy(void) +{ +#ifdef CONFIG_TARGET_LS1012ARDB + /* Through reset IO expander reset both RGMII and SGMII PHYs */ +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + /* + * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0). + */ + ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + 0); + return; + } + /* Config port 0 + * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B + * are enabled as an output. + */ + dm_i2c_reg_write(dev, 6, __PHY_MASK); + + /* + * Set port 0 output a value to reset ETH2 interface + * - pin IOXP_RST_ETH2_B output 0b0 + */ + dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK); + mdelay(10); + dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK); + /* + * Set port 0 output a value to reset ETH1 interface + * - pin IOXP_RST_ETH1_B output 0b0 + */ + mdelay(10); + dm_i2c_reg_write(dev, 2, 0xFF); +#else + i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); + mdelay(10); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK); + mdelay(10); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); +#endif + mdelay(50); +#endif +} + +int pfe_eth_board_init(struct udevice *dev) +{ + static int init_done; + struct mii_dev *bus; + struct pfe_mdio_info mac_mdio_info; + struct pfe_eth_dev *priv = dev_get_priv(dev); + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + int srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (!init_done) { + ls1012ardb_reset_phy(); + mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + init_done = 1; + } + + pfe_set_mdio(priv->gemac_port, + miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + + switch (srds_s1) { + case 0x3508: + if (!priv->gemac_port) { + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + } else { + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_RGMII_ID); + } + break; + case 0x2208: + if (!priv->gemac_port) { + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII_2500); + } else { + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII_2500); + } + break; + default: + printf("unsupported SerDes PRCTL= %d\n", srds_s1); + break; + } + return 0; +} + +static struct pfe_eth_pdata pfe_pdata0 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC1_BASE_ADDR, + .phy_interface = 0, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +static struct pfe_eth_pdata pfe_pdata1 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC2_BASE_ADDR, + .phy_interface = 1, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +U_BOOT_DRVINFO(ls1012a_pfe0) = { + .name = "pfe_eth", + .plat = &pfe_pdata0, +}; + +U_BOOT_DRVINFO(ls1012a_pfe1) = { + .name = "pfe_eth", + .plat = &pfe_pdata1, +}; diff --git a/roms/u-boot/board/freescale/ls1012ardb/ls1012ardb.c b/roms/u-boot/board/freescale/ls1012ardb/ls1012ardb.c new file mode 100644 index 000000000..62e8af48c --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012ardb/ls1012ardb.c @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <command.h> +#include <fdt_support.h> +#include <hang.h> +#include <i2c.h> +#include <asm/cache.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif +#include <asm/arch/mmu.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fsl_esdhc.h> +#include <env_internal.h> +#include <fsl_mmdc.h> +#include <netdev.h> +#include <fsl_sec.h> +#include <net/pfe_eth/pfe/pfe_hw.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BOOT_FROM_UPPER_BANK 0x2 +#define BOOT_FROM_LOWER_BANK 0x1 + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_LS1012ARDB + u8 in1; + int ret, bus_num = 0; + + puts("Board: LS1012ARDB "); + + /* Initialize i2c early for Serial flash bank information */ +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1); +#endif + if (ret < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + + puts("Version"); + switch (in1 & SW_REV_MASK) { + case SW_REV_A: + puts(": RevA"); + break; + case SW_REV_B: + puts(": RevB"); + break; + case SW_REV_C: + puts(": RevC"); + break; + case SW_REV_C1: + puts(": RevC1"); + break; + case SW_REV_C2: + puts(": RevC2"); + break; + case SW_REV_D: + puts(": RevD"); + break; + case SW_REV_E: + puts(": RevE"); + break; + default: + puts(": unknown"); + break; + } + + printf(", boot from QSPI"); + if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU) + puts(": emu\n"); + else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1) + puts(": bank1\n"); + else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2) + puts(": bank2\n"); + else + puts("unknown\n"); +#else + + puts("Board: LS1012A2G5RDB "); +#endif + return 0; +} + +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} +#else +int dram_init(void) +{ +#ifndef CONFIG_TFABOOT + static const struct fsl_mmdc_info mparam = { + 0x05180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); +#endif + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} +#endif + + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; +} + +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + +#ifdef CONFIG_TARGET_LS1012ARDB +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc1_path[] = "/soc/esdhc@1580000"; + bool sdhc2_en = false; + u8 mux_sdhc2; + u8 io = 0; + int ret, bus_num = 0; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1); +#else + i2c_set_bus_num(bus_num); + /* IO1[7:3] is the field of board revision info. */ + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1); +#endif + if (ret < 0) { + printf("Error reading i2c boot information!\n"); + return 0; + } + + /* hwconfig method is used for RevD and later versions. */ + if ((io & SW_REV_MASK) <= SW_REV_D) { +#ifdef CONFIG_HWCONFIG + if (hwconfig("esdhc1")) + sdhc2_en = true; +#endif + } else { + /* + * The I2C IO-expander for mux select is used to control + * the muxing of various onboard interfaces. + * + * IO0[3:2] indicates SDHC2 interface demultiplexer + * select lines. + * 00 - SDIO wifi + * 01 - GPIO (to Arduino) + * 10 - eMMC Memory + * 11 - SPI + */ +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1); +#else + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1); +#endif + if (ret < 0) { + printf("Error reading i2c boot information!\n"); + return 0; + } + + mux_sdhc2 = (io & 0x0c) >> 2; + /* Enable SDHC2 only when use SDIO wifi and eMMC */ + if (mux_sdhc2 == 2 || mux_sdhc2 == 0) + sdhc2_en = true; + } + if (sdhc2_en) + do_fixup_by_path(blob, esdhc1_path, "status", "okay", + sizeof("okay"), 1); + else + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + return 0; +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} + +static int switch_to_bank1(void) +{ + u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03; + int ret, bus_num = 0; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + /* + * -------------------------------------------------------------------- + * |bus |I2C address| Device | Notes | + * -------------------------------------------------------------------- + * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General | + * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output| + * | | | KW41GPIO) - NXP | (GPIO) expansion for the | + * | | | PCAL9555AHF | I2C bus | + * ----- -------------------------------------------------------------- + * - mount three IO expander(PCAL9555AHF) on I2C1 + * + * PCAL9555A device address + * slave address + * -------------------------------------- + * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W | + * -------------------------------------- + * | fixed | hardware selectable| + * + * Output port 1(Pinter register bits = 0x03) + * + * P1_[7~0] = 0xf4 + * P1_0 <---> CFG_MUX_QSPI_S0 + * P1_1 <---> CFG_MUX_QSPI_S1 + * CFG_MUX_QSPI_S[1:0] = 0b00 + * + * QSPI chip-select demultiplexer select + * --------------------------------------------------------------------- + * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values + * --------------------------------------------------------------------- + * 0 | 0 |CS routed to SPI memory bank1(default) + * --------------------------------------------------------------------- + * 0 | 1 |CS routed to SPI memory bank2 + * --------------------------------------------------------------------- + * + */ + ret = dm_i2c_write(dev, offset_addr, &data, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_write(chip_addr, offset_addr, 1, &data, 1); +#endif + + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + chip_addr, offset_addr, data); + } + + return ret; +} + +static int switch_to_bank2(void) +{ + u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3}; + u8 chip_addr = 0x24; + int ret, i, bus_num = 0; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); +#endif + + /* + * 1th step: config port 1 + * - the port 1 pin is enabled as an output + * 2th step: output port 1 + * - P1_[7:0] output 0xf5, + * then CFG_MUX_QSPI_S[1:0] equal to 0b01, + * CS routed to SPI memory bank2 + */ + for (i = 0; i < sizeof(data); i++) { +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1); +#else /* Non DM I2C support - will be removed */ + ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1); +#endif + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + chip_addr, offset_addr[i], data[i]); + goto err; + } + } + +err: + return ret; +} + +static int convert_flash_bank(int bank) +{ + int ret = 0; + + switch (bank) { + case BOOT_FROM_UPPER_BANK: + ret = switch_to_bank2(); + break; + case BOOT_FROM_LOWER_BANK: + ret = switch_to_bank1(); + break; + default: + ret = CMD_RET_USAGE; + break; + }; + + return ret; +} + +static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else if (strcmp(argv[1], "2") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)" +); 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