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-rw-r--r--roms/u-boot/board/freescale/mx51evk/Kconfig15
-rw-r--r--roms/u-boot/board/freescale/mx51evk/MAINTAINERS7
-rw-r--r--roms/u-boot/board/freescale/mx51evk/Makefile8
-rw-r--r--roms/u-boot/board/freescale/mx51evk/imximage.cfg108
-rw-r--r--roms/u-boot/board/freescale/mx51evk/mx51evk.c218
-rw-r--r--roms/u-boot/board/freescale/mx51evk/mx51evk_video.c98
6 files changed, 454 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/mx51evk/Kconfig b/roms/u-boot/board/freescale/mx51evk/Kconfig
new file mode 100644
index 000000000..f9b69cbd6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX51EVK
+
+config SYS_BOARD
+ default "mx51evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx51evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx51evk/MAINTAINERS b/roms/u-boot/board/freescale/mx51evk/MAINTAINERS
new file mode 100644
index 000000000..1ca55f7d1
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX51EVK BOARD
+M: Fabio Estevam <festevam@gmail.com>
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/freescale/mx51evk/
+F: include/configs/mx51evk.h
+F: configs/mx51evk_defconfig
diff --git a/roms/u-boot/board/freescale/mx51evk/Makefile b/roms/u-boot/board/freescale/mx51evk/Makefile
new file mode 100644
index 000000000..1a9581cab
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+
+obj-y += mx51evk.o
+obj-$(CONFIG_VIDEO) += mx51evk_video.o
diff --git a/roms/u-boot/board/freescale/mx51evk/imximage.cfg b/roms/u-boot/board/freescale/mx51evk/imximage.cfg
new file mode 100644
index 000000000..ff2ec4aa2
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/imximage.cfg
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Setting IOMUXC */
+DATA 4 0x73FA88a0 0x200
+DATA 4 0x73FA850c 0x20c5
+DATA 4 0x73FA8510 0x20c5
+DATA 4 0x73FA883c 0x2
+DATA 4 0x73FA8848 0x2
+DATA 4 0x73FA84b8 0xe7
+DATA 4 0x73FA84bc 0x45
+DATA 4 0x73FA84c0 0x45
+DATA 4 0x73FA84c4 0x45
+DATA 4 0x73FA84c8 0x45
+DATA 4 0x73FA8820 0x0
+DATA 4 0x73FA84a4 0x3
+DATA 4 0x73FA84a8 0x3
+DATA 4 0x73FA84ac 0xe3
+DATA 4 0x73FA84b0 0xe3
+DATA 4 0x73FA84b4 0xe3
+DATA 4 0x73FA84cc 0xe3
+DATA 4 0x73FA84d0 0xe2
+
+DATA 4 0x73FA882c 0x6
+DATA 4 0x73FA88a4 0x6
+DATA 4 0x73FA88ac 0x6
+DATA 4 0x73FA88b8 0x6
+
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
+DATA 4 0x83FD9000 0x82a20000
+/* ESDCTL_ESDCTL1 */
+DATA 4 0x83FD9008 0x82a20000
+/* ESDCTL_ESDMISC */
+DATA 4 0x83FD9010 0x000ad0d0
+/* ESDCTL_ESDCFG0 */
+DATA 4 0x83FD9004 0x333574aa
+/* ESDCTL_ESDCFG1 */
+DATA 4 0x83FD900C 0x333574aa
+
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x0000801a
+DATA 4 0x83FD9014 0x0000801b
+DATA 4 0x83FD9014 0x00448019
+DATA 4 0x83FD9014 0x07328018
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x06328018
+DATA 4 0x83FD9014 0x03808019
+DATA 4 0x83FD9014 0x00408019
+DATA 4 0x83FD9014 0x00008000
+
+/* Init DRAM on CS1 */
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x0000801e
+DATA 4 0x83FD9014 0x0000801f
+DATA 4 0x83FD9014 0x0000801d
+DATA 4 0x83FD9014 0x0732801c
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x0632801c
+DATA 4 0x83FD9014 0x0380801d
+DATA 4 0x83FD9014 0x0040801d
+DATA 4 0x83FD9014 0x00008004
+
+/* Write to CTL0 */
+DATA 4 0x83FD9000 0xb2a20000
+/* Write to CTL1 */
+DATA 4 0x83FD9008 0xb2a20000
+/* ESDMISC */
+DATA 4 0x83FD9010 0x000ad6d0
+/* ESDCTL_ESDCDLYGD */
+DATA 4 0x83FD9034 0x90000000
+DATA 4 0x83FD9014 0x00000000
diff --git a/roms/u-boot/board/freescale/mx51evk/mx51evk.c b/roms/u-boot/board/freescale/mx51evk/mx51evk.c
new file mode 100644
index 000000000..c8439a634
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/mx51evk.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx51.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <i2c.h>
+#include <input.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ u32 rev = get_cpu_rev();
+ if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
+ rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
+ return rev;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+ static const iomux_v3_cfg_t spi_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
+ MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+#endif
+
+static void power_init(void)
+{
+ unsigned int val;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
+ if (ret)
+ return;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return;
+
+ /* Write needed to Power Gate 2 register */
+ pmic_reg_read(p, REG_POWER_MISC, &val);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(p, REG_POWER_MISC, val);
+
+ /* Externally powered */
+ pmic_reg_read(p, REG_CHARGE, &val);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(p, REG_CHARGE, val);
+
+ /* power up the system first */
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+ pmic_reg_write(p, REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ pmic_reg_read(p, REG_SW_2, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_2, val);
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, &mxc_ccm->cacrr);
+
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ pmic_reg_read(p, REG_SETTING_1, &val);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+ pmic_reg_write(p, REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(p, REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
+ NO_PAD_CTRL));
+ gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14");
+ gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
+
+ udelay(500);
+
+ gpio_set_value(IMX_GPIO_NR(2, 14), 1);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_lcd();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_MXC_SPI
+ setup_iomux_spi();
+ power_init();
+#endif
+
+ return 0;
+}
+#endif
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX51EVK\n");
+
+ return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx51evk/mx51evk_video.c b/roms/u-boot/board/freescale/mx51evk/mx51evk_video.c
new file mode 100644
index 000000000..3715c5d73
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/mx51evk_video.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx51.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9)
+#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10)
+#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4)
+
+static struct fb_videomode const claa_wvga = {
+ .name = "CLAA07LC0ACW",
+ .refresh = 57,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 37037,
+ .left_margin = 40,
+ .right_margin = 60,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode const dvi = {
+ .name = "DVI panel",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+void setup_iomux_lcd(void)
+{
+ /* DI2_PIN15 */
+ imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15);
+
+ /* Pad settings for DI2_DISP_CLK */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK,
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW));
+
+ /* Turn on 3.3V voltage for LCD */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9,
+ NO_PAD_CTRL));
+ gpio_direction_output(MX51EVK_LCD_3V3, 1);
+
+ /* Turn on 5V voltage for LCD */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10,
+ NO_PAD_CTRL));
+ gpio_direction_output(MX51EVK_LCD_5V, 1);
+
+ /* Turn on GPIO backlight */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4,
+ NO_PAD_CTRL));
+ gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
+}
+
+int board_video_skip(void)
+{
+ int ret;
+ char const *e = env_get("panel");
+
+ if (e) {
+ if (strcmp(e, "claa") == 0) {
+ ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
+ if (ret)
+ printf("claa cannot be configured: %d\n", ret);
+ return ret;
+ }
+ }
+
+ /*
+ * 'panel' env variable not found or has different value than 'claa'
+ * Defaulting to dvi output.
+ */
+ ret = ipuv3_fb_init(&dvi, 0, IPU_PIX_FMT_RGB24);
+ if (ret)
+ printf("dvi cannot be configured: %d\n", ret);
+ return ret;
+}