diff options
Diffstat (limited to 'roms/u-boot/board/freescale/t4rdb')
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/Kconfig | 14 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/MAINTAINERS | 8 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/Makefile | 19 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/cpld.c | 129 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/cpld.h | 48 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/ddr.c | 128 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/ddr.h | 77 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/eth.c | 152 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/law.c | 30 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/pci.c | 25 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/spl.c | 98 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/t4240rdb.c | 153 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/t4_pbi.cfg | 27 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/t4_sd_rcw.cfg | 7 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/t4rdb.h | 17 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/t4rdb/tlb.c | 123 |
16 files changed, 1055 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/t4rdb/Kconfig b/roms/u-boot/board/freescale/t4rdb/Kconfig new file mode 100644 index 000000000..a94a57e7f --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/Kconfig @@ -0,0 +1,14 @@ +if TARGET_T4160RDB || TARGET_T4240RDB + +config SYS_BOARD + default "t4rdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T4240RDB" + +source "board/freescale/common/Kconfig" + +endif diff --git a/roms/u-boot/board/freescale/t4rdb/MAINTAINERS b/roms/u-boot/board/freescale/t4rdb/MAINTAINERS new file mode 100644 index 000000000..7380408aa --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/MAINTAINERS @@ -0,0 +1,8 @@ +T4RDB BOARD +M: Priyanka Jain <priyanka.jain@nxp.com> +S: Maintained +F: board/freescale/t4rdb/ +F: include/configs/T4240RDB.h +F: configs/T4160RDB_defconfig +F: configs/T4240RDB_defconfig +F: configs/T4240RDB_SDCARD_defconfig diff --git a/roms/u-boot/board/freescale/t4rdb/Makefile b/roms/u-boot/board/freescale/t4rdb/Makefile new file mode 100644 index 000000000..209983a24 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/Makefile @@ -0,0 +1,19 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o +obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o +obj-y += cpld.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o +endif + +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/roms/u-boot/board/freescale/t4rdb/cpld.c b/roms/u-boot/board/freescale/t4rdb/cpld.c new file mode 100644 index 000000000..d484509bc --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/cpld.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan <Chunhe.Lan@freescale.com> + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 val, curbank, altbank, override; + + val = CPLD_READ(vbank); + curbank = val & CPLD_BANK_SEL_MASK; + + switch (curbank) { + case CPLD_SELECT_BANK0: + case CPLD_SELECT_BANK4: + altbank = CPLD_SELECT_BANK4; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + default: + printf("CPLD Altbank Fail: Invalid value!\n"); + return; + } +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 val; + + val = CPLD_DEFAULT_BANK; + + CPLD_WRITE(global_reset, val); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); + printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); + printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); + printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("software_on = 0x%02x\n", CPLD_READ(software_on)); + printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); + printf("res0 = 0x%02x\n", CPLD_READ(res0)); + printf("vbank = 0x%02x\n", CPLD_READ(vbank)); + printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); + printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); + printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); + printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); + printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); + printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); + printf("res1 = 0x%02x\n", CPLD_READ(res1)); + putc('\n'); +} +#endif + +#ifndef CONFIG_SPL_BUILD +int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/roms/u-boot/board/freescale/t4rdb/cpld.h b/roms/u-boot/board/freescale/t4rdb/cpld.h new file mode 100644 index 000000000..dc3f9f3c2 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/cpld.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan <Chunhe.Lan@freescale.com> + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ + u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ + u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ + u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ + u8 hw_ver; /* 0x04 - PCBA Version Register */ + u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ + u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ + u8 res0; /* 0x07 - not used */ + u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ + u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ + u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ + u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ + u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ + u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ + u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ + u8 res1; /* 0x0f - not used */ +}; + +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_EN 0x04 +#define CPLD_SYSTEM_RESET 0x01 +#define CPLD_SELECT_BANK0 0x00 +#define CPLD_SELECT_BANK4 0x04 +#define CPLD_DEFAULT_BANK 0x01 + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + diff --git a/roms/u-boot/board/freescale/t4rdb/ddr.c b/roms/u-boot/board/freescale/t4rdb/ddr.c new file mode 100644 index 000000000..57cbde154 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/ddr.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <init.h> +#include <log.h> +#include <asm/global_data.h> +#include <asm/mmu.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data\n" + "rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x64; +} + +int dram_init(void) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + dram_size = fsl_ddr_sdram(); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + gd->ram_size = dram_size; + + return 0; +} diff --git a/roms/u-boot/board/freescale/t4rdb/ddr.h b/roms/u-boot/board/freescale/t4rdb/ddr.h new file mode 100644 index 000000000..74a277961 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/ddr.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a}, + {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09}, + {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b}, + {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a}, + {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a}, + {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a}, + {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/roms/u-boot/board/freescale/t4rdb/eth.c b/roms/u-boot/board/freescale/t4rdb/eth.c new file mode 100644 index 000000000..c815a3a4f --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/eth.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Chunhe Lan <Chunhe.Lan@freescale.com> + */ + +#include <common.h> +#include <command.h> +#include <fdt_support.h> +#include <net.h> +#include <netdev.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <fsl_dtsec.h> +#include <asm/fsl_serdes.h> +#include <hwconfig.h> + +#include "../common/fman.h" +#include "t4rdb.h" + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +int board_eth_init(struct bd_info *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { + /* SGMII */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); + } else { + puts("Invalid SerDes1 protocol for T4240RDB\n"); + } + + fm_disable_port(FM1_DTSEC5); + fm_disable_port(FM1_DTSEC6); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { + /* SGMII && XFI */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); + } else { + puts("Invalid SerDes2 protocol for T4240RDB\n"); + } + + fm_disable_port(FM2_DTSEC5); + fm_disable_port(FM2_DTSEC6); + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/roms/u-boot/board/freescale/t4rdb/law.c b/roms/u-boot/board/freescale/t4rdb/law.c new file mode 100644 index 000000000..038f60565 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/law.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/roms/u-boot/board/freescale/t4rdb/pci.c b/roms/u-boot/board/freescale/t4rdb/pci.c new file mode 100644 index 000000000..c2bc05164 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/pci.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <command.h> +#include <init.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <linux/libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +#if !defined(CONFIG_DM_PCI) +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, struct bd_info *bd) +{ + FT_FSL_PCI_SETUP; +} +#endif diff --git a/roms/u-boot/board/freescale/t4rdb/spl.c b/roms/u-boot/board/freescale/t4rdb/spl.c new file mode 100644 index 000000000..e2f9c9b3d --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/spl.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * Author: Chunhe Lan <Chunhe.Lan@freescale.com> + */ + +#include <common.h> +#include <clock_legacy.h> +#include <console.h> +#include <env_internal.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> + +#include "t4rdb.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + + puts("\nSD boot...\n"); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + struct bd_info *bd; + + bd = (struct bd_info *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); + + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; + + i2c_init_all(); + + dram_init(); + + mmc_boot(); +} diff --git a/roms/u-boot/board/freescale/t4rdb/t4240rdb.c b/roms/u-boot/board/freescale/t4rdb/t4240rdb.c new file mode 100644 index 000000000..6ab35ca91 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/t4240rdb.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <command.h> +#include <env.h> +#include <fdt_support.h> +#include <i2c.h> +#include <image.h> +#include <init.h> +#include <netdev.h> +#include <asm/global_data.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> + +#include "t4rdb.h" +#include "cpld.h" +#include "../common/vid.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + u8 sw; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + + puts("SERDES Reference Clocks:\n"); + printf(" SERDES1=100MHz SERDES2=156.25MHz\n" + " SERDES3=100MHz SERDES4=100MHz\n"); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fsl_fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif + fdt_fixup_board_enet(blob); +#endif + + return 0; +} + +/* + * This function is called by bdinfo to print detail board information. + * As an exmaple for future board, we organize the messages into + * several sections. If applicable, the message is in the format of + * <name> = <value> + * It should aligned with normal output of bdinfo command. + * + * Voltage: Core, DDR and another configurable voltages + * Clock : Critical clocks which are not printed already + * RCW : RCW source if not printed already + * Misc : Other important information not in above catagories + */ +void board_detail(void) +{ + int rcwsrc; + + /* RCW section SW3[4] */ + rcwsrc = 0x0; + puts("RCW source = "); + switch (rcwsrc & 0x1) { + case 0x1: + puts("SDHC/eMMC\n"); + break; + default: + puts("I2C normal addressing\n"); + break; + } +} diff --git a/roms/u-boot/board/freescale/t4rdb/t4_pbi.cfg b/roms/u-boot/board/freescale/t4rdb/t4_pbi.cfg new file mode 100644 index 000000000..0b326fa16 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/t4_pbi.cfg @@ -0,0 +1,27 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +091380c0 00100000 diff --git a/roms/u-boot/board/freescale/t4rdb/t4_sd_rcw.cfg b/roms/u-boot/board/freescale/t4rdb/t4_sd_rcw.cfg new file mode 100644 index 000000000..cc2bff682 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/t4_sd_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#serdes protocol 27_55_1_9 +16070019 18101916 00000000 00000000 +6c6e0848 00448c00 6c020000 f5000000 +00000000 ee0000ee 00000000 000307fc +00000000 00000000 00000000 00000028 diff --git a/roms/u-boot/board/freescale/t4rdb/t4rdb.h b/roms/u-boot/board/freescale/t4rdb/t4rdb.h new file mode 100644 index 000000000..3f1fa7bbd --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/t4rdb.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __T4RDB_H__ +#define __T4RDB_H__ + +#undef CONFIG_SYS_NUM_FM1_DTSEC +#undef CONFIG_SYS_NUM_FM2_DTSEC +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, struct bd_info *bd); + +#endif diff --git a/roms/u-boot/board/freescale/t4rdb/tlb.c b/roms/u-boot/board/freescale/t4rdb/tlb.c new file mode 100644 index 000000000..b927dd848 --- /dev/null +++ b/roms/u-boot/board/freescale/t4rdb/tlb.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 512K SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_512K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#endif + +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 18, BOOKE_PAGESZ_2G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); |