diff options
Diffstat (limited to 'roms/u-boot/board/gdsys/mpc8308')
| -rw-r--r-- | roms/u-boot/board/gdsys/mpc8308/Kconfig | 83 | ||||
| -rw-r--r-- | roms/u-boot/board/gdsys/mpc8308/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/gdsys/mpc8308/Makefile | 7 | ||||
| -rw-r--r-- | roms/u-boot/board/gdsys/mpc8308/gazerbeam.c | 186 | ||||
| -rw-r--r-- | roms/u-boot/board/gdsys/mpc8308/mpc8308.c | 122 | ||||
| -rw-r--r-- | roms/u-boot/board/gdsys/mpc8308/mpc8308.h | 13 | ||||
| -rw-r--r-- | roms/u-boot/board/gdsys/mpc8308/sdram.c | 89 |
7 files changed, 506 insertions, 0 deletions
diff --git a/roms/u-boot/board/gdsys/mpc8308/Kconfig b/roms/u-boot/board/gdsys/mpc8308/Kconfig new file mode 100644 index 000000000..c3fd0518b --- /dev/null +++ b/roms/u-boot/board/gdsys/mpc8308/Kconfig @@ -0,0 +1,83 @@ +if TARGET_GAZERBEAM + +config GDSYS_LEGACY_OSD_CMDS + bool + help + Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by + gdsys devices. + +config GDSYS_LEGACY_DRIVERS + bool + help + Enable the gdsys legacy drivers under board/gdsys/common. If this + option is not set, all relevant DM drivers must be configured for the + device in question. + +config SYS_FPGA0_BASE + hex + default E0600000 + help + The base address of the first FPGA's register map. + +config SYS_FPGA0_SIZE + hex + default 1 + help + The base address of the first FPGA's register map. + +config SYS_FPGA1_BASE + hex + help + The base address of the second FPGA's register map. + +config SYS_FPGA1_SIZE + hex + help + The base address of the second FPGA's register map. + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "gazerbeam" + +config SYS_FPGA1_BASE + default E0700000 + +config SYS_FPGA1_SIZE + default 1 + +config GDSYS_LEGACY_OSD_CMDS + default y + +choice + prompt "FPGA flavor selection" + +config SYS_FPGA_FLAVOR_LEGACY + bool "Legacy flavor" + help + This enables support for the gdsys pre-Gazerbeam FPGA memory layout. + +config SYS_FPGA_FLAVOR_GAZERBEAM + bool "Gazerbeam flavor" + help + This enables support for the gdsys FPGA memory layout of the + Gazerbeam board. + +endchoice + +config EXTENDED_FEATURES + bool "FPGA extended features" + depends on GDSYS_LEGACY_DRIVERS + help + Enable support for the extended features field of the IHS FPGA. + +config CMD_IOLOOP + bool "Enable 'ioloop' and 'ioreflect' commands" + help + These commands provide FPGA tests. + +endif diff --git a/roms/u-boot/board/gdsys/mpc8308/MAINTAINERS b/roms/u-boot/board/gdsys/mpc8308/MAINTAINERS new file mode 100644 index 000000000..dc0b389f7 --- /dev/null +++ b/roms/u-boot/board/gdsys/mpc8308/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8308 BOARD +M: Dirk Eibach <dirk.eibach@gdsys.cc> +S: Maintained +F: board/gdsys/mpc8308/ +F: include/configs/gazerbeam.h +F: configs/gazerbeam_defconfig diff --git a/roms/u-boot/board/gdsys/mpc8308/Makefile b/roms/u-boot/board/gdsys/mpc8308/Makefile new file mode 100644 index 000000000..f86d997bc --- /dev/null +++ b/roms/u-boot/board/gdsys/mpc8308/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2014 +# Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + +obj-y := mpc8308.o sdram.o +obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/roms/u-boot/board/gdsys/mpc8308/gazerbeam.c b/roms/u-boot/board/gdsys/mpc8308/gazerbeam.c new file mode 100644 index 000000000..3d4a7e57f --- /dev/null +++ b/roms/u-boot/board/gdsys/mpc8308/gazerbeam.c @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <dm.h> +#include <env.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <init.h> +#include <miiphy.h> +#include <misc.h> +#include <sysinfo.h> +#include <tpm-v1.h> +#include <video_osd.h> +#include <asm/global_data.h> + +#include "../common/ihs_mdio.h" +#include "../../../drivers/sysinfo/gazerbeam.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct ihs_mdio_info ihs_mdio_info[] = { + { .fpga = NULL, .name = "ihs0", .base = 0x58 }, + { .fpga = NULL, .name = "ihs1", .base = 0x58 }, +}; + +static int get_tpm(struct udevice **devp) +{ + int rc; + + rc = uclass_first_device_err(UCLASS_TPM, devp); + if (rc) { + printf("Could not find TPM (ret=%d)\n", rc); + return CMD_RET_FAILURE; + } + + return 0; +} + +int board_early_init_r(void) +{ + struct udevice *sysinfo; + struct udevice *serdes; + int mc = 0; + int con = 0; + + if (sysinfo_get(&sysinfo)) + puts("Could not find sysinfo information device.\n"); + + /* Initialize serdes */ + uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, "serdes", &serdes); + + if (sysinfo_detect(sysinfo)) + puts("Device information detection failed.\n"); + + sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc); + sysinfo_get_int(sysinfo, BOARD_VARIANT, &con); + + if (mc == 2 || mc == 1) + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22"); + + if (mc == 4) { + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20"); + dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0"); + dev_enable_by_path("/fpga1bus"); + } + + if (mc == 2 || con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video1"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video1"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video1"); + } + + if (con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video0"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video0"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video0"); + } + + return 0; +} + +int checksysinfo(void) +{ + struct udevice *sysinfo; + char *s = env_get("serial#"); + int mc = 0; + int con = 0; + + if (sysinfo_get(&sysinfo)) + puts("Could not find sysinfo information device.\n"); + + sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc); + sysinfo_get_int(sysinfo, BOARD_VARIANT, &con); + + puts("Board: Gazerbeam "); + printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC"); + printf("%s", con == VAR_CON ? "CON" : "CPU"); + + if (s) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void display_osd_info(struct udevice *osd, + struct video_osd_info *osd_info) +{ + printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n", + osd->name, osd_info->major_version, osd_info->minor_version, + osd_info->width, osd_info->height); +} + +int last_stage_init(void) +{ + int fpga_hw_rev = 0; + int i; + struct udevice *sysinfo; + struct udevice *osd; + struct video_osd_info osd_info; + struct udevice *tpm; + int ret; + + if (sysinfo_get(&sysinfo)) + puts("Could not find sysinfo information device.\n"); + + if (sysinfo) { + int res = sysinfo_get_int(sysinfo, BOARD_HWVERSION, + &fpga_hw_rev); + + if (res) + printf("Could not determind FPGA HW revision (res = %d)\n", + res); + } + + env_set_ulong("fpga_hw_rev", fpga_hw_rev); + + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR) || + tpm1_continue_self_test(tpm)) { + printf("TPM init failed\n"); + } + + if (fpga_hw_rev >= 4) { + for (i = 0; i < 4; i++) { + struct udevice *rxaui; + char name[8]; + + snprintf(name, sizeof(name), "rxaui%d", i); + /* Disable RXAUI polarity inversion */ + ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, + name, &rxaui); + if (!ret) + misc_set_enabled(rxaui, false); + } + } + + for (uclass_first_device(UCLASS_VIDEO_OSD, &osd); + osd; + uclass_next_device(&osd)) { + video_osd_get_info(osd, &osd_info); + display_osd_info(osd, &osd_info); + } + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + fsl_fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif diff --git a/roms/u-boot/board/gdsys/mpc8308/mpc8308.c b/roms/u-boot/board/gdsys/mpc8308/mpc8308.c new file mode 100644 index 000000000..0f90f8ad3 --- /dev/null +++ b/roms/u-boot/board/gdsys/mpc8308/mpc8308.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + */ + +#include <common.h> +#include <command.h> +#include <init.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/global_data.h> +#include <linux/delay.h> + +#include "mpc8308.h" +#include <gdsys_fpga.h> + +#define REFLECTION_TESTPATTERN 0xdede +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) + +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS +/* as gpio output status cannot be read back, we have to buffer it locally */ +u32 gpio0_out; + +void setbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out |= mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + +void clrbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out &= ~mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + +int get_fpga_state(uint dev) +{ + return gd->arch.fpga_state[dev]; +} + +int board_early_init_f(void) +{ + uint k; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + return 0; +} + +int board_early_init_r(void) +{ + uint k; + uint ctr; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + /* + * reset FPGA + */ + mpc8308_init(); + + mpc8308_set_fpga_reset(1); + + mpc8308_setup_hw(); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!mpc8308_get_fpga_done(k)) { + mdelay(100); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_DONE_FAILED; + break; + } + } + } + + udelay(10); + + mpc8308_set_fpga_reset(0); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + /* + * wait for fpga out of reset + */ + ctr = 0; + while (1) { + u16 val; + + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); + + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) + break; + + mdelay(100); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } + } + } + + return 0; +} +#endif diff --git a/roms/u-boot/board/gdsys/mpc8308/mpc8308.h b/roms/u-boot/board/gdsys/mpc8308/mpc8308.h new file mode 100644 index 000000000..1e4f24fb2 --- /dev/null +++ b/roms/u-boot/board/gdsys/mpc8308/mpc8308.h @@ -0,0 +1,13 @@ +#ifndef __MPC8308_H_ +#define __MPC8308_H_ + +void setbits_gpio0_out(u32 mask); +void clrbits_gpio0_out(u32 mask); + +/* functions to be provided by board implementation */ +void mpc8308_init(void); +void mpc8308_set_fpga_reset(unsigned state); +void mpc8308_setup_hw(void); +int mpc8308_get_fpga_done(unsigned fpga); + +#endif /* __MPC8308_H_ */ diff --git a/roms/u-boot/board/gdsys/mpc8308/sdram.c b/roms/u-boot/board/gdsys/mpc8308/sdram.c new file mode 100644 index 000000000..bfd55f54e --- /dev/null +++ b/roms/u-boot/board/gdsys/mpc8308/sdram.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * + * This files is mostly identical to the original from + * board\freescale\mpc8315erdb\sdram.c + */ + +#ifndef CONFIG_MPC83XX_SDRAM + +#include <common.h> +#include <init.h> +#include <mpc83xx.h> +#include <spd_sdram.h> + +#include <asm/bitops.h> +#include <asm/global_data.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_SDRAM_BASE & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); +} + +int dram_init(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -ENXIO; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + /* return total bus SDRAM size(bytes) -- DDR */ + gd->ram_size = msize; + + return 0; +} + +#endif /* !CONFIG_MPC83XX_SDRAM */ |