diff options
Diffstat (limited to 'roms/u-boot/board/intel/galileo')
| -rw-r--r-- | roms/u-boot/board/intel/galileo/.gitignore | 3 | ||||
| -rw-r--r-- | roms/u-boot/board/intel/galileo/Kconfig | 25 | ||||
| -rw-r--r-- | roms/u-boot/board/intel/galileo/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/intel/galileo/Makefile | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/intel/galileo/acpi/mainboard.asl | 10 | ||||
| -rw-r--r-- | roms/u-boot/board/intel/galileo/dsdt.asl | 13 | ||||
| -rw-r--r-- | roms/u-boot/board/intel/galileo/galileo.c | 61 |
7 files changed, 124 insertions, 0 deletions
diff --git a/roms/u-boot/board/intel/galileo/.gitignore b/roms/u-boot/board/intel/galileo/.gitignore new file mode 100644 index 000000000..6eb8a5481 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/roms/u-boot/board/intel/galileo/Kconfig b/roms/u-boot/board/intel/galileo/Kconfig new file mode 100644 index 000000000..fb8d94fb5 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/Kconfig @@ -0,0 +1,25 @@ +if TARGET_GALILEO + +config SYS_BOARD + default "galileo" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "quark" + +config SYS_CONFIG_NAME + default "galileo" + +config SYS_TEXT_BASE + default 0xfff10000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_QUARK + select BOARD_ROMSIZE_KB_1024 + select SPI_FLASH_WINBOND + +endif diff --git a/roms/u-boot/board/intel/galileo/MAINTAINERS b/roms/u-boot/board/intel/galileo/MAINTAINERS new file mode 100644 index 000000000..dbbc82e8a --- /dev/null +++ b/roms/u-boot/board/intel/galileo/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL GALILEO BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/galileo/ +F: include/configs/galileo.h +F: configs/galileo_defconfig diff --git a/roms/u-boot/board/intel/galileo/Makefile b/roms/u-boot/board/intel/galileo/Makefile new file mode 100644 index 000000000..4130bb023 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + +obj-y += galileo.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/roms/u-boot/board/intel/galileo/acpi/mainboard.asl b/roms/u-boot/board/intel/galileo/acpi/mainboard.asl new file mode 100644 index 000000000..beb9d93ec --- /dev/null +++ b/roms/u-boot/board/intel/galileo/acpi/mainboard.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/roms/u-boot/board/intel/galileo/dsdt.asl b/roms/u-boot/board/intel/galileo/dsdt.asl new file mode 100644 index 000000000..d2297ef59 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/dsdt.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/roms/u-boot/board/intel/galileo/galileo.c b/roms/u-boot/board/intel/galileo/galileo.c new file mode 100644 index 000000000..341b627a6 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/galileo.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/device.h> +#include <asm/arch/quark.h> + +/* + * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin. + * + * We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this + * pin, as these APIs will eventually call into gpio_ich6_of_to_plat() + * in the Intel ICH6 GPIO driver where it calls PCI configuration space access + * APIs which will trigger PCI enumeration process. + * + * Check <asm/arch-quark/quark.h> for more details. + */ +void board_assert_perst(void) +{ + u32 base, port, val; + + /* retrieve the GPIO IO base */ + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); + base = (base & 0xffff) & ~0x7f; + + /* enable the pin */ + port = base + 0x20; + val = inl(port); + val |= (1 << 0); + outl(val, port); + + /* configure the pin as output */ + port = base + 0x24; + val = inl(port); + val &= ~(1 << 0); + outl(val, port); + + /* pull it down (assert) */ + port = base + 0x28; + val = inl(port); + val &= ~(1 << 0); + outl(val, port); +} + +void board_deassert_perst(void) +{ + u32 base, port, val; + + /* retrieve the GPIO IO base */ + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); + base = (base & 0xffff) & ~0x7f; + + /* pull it up (de-assert) */ + port = base + 0x28; + val = inl(port); + val |= (1 << 0); + outl(val, port); +} |