diff options
Diffstat (limited to 'roms/u-boot/board/isee/igep00x0')
| -rw-r--r-- | roms/u-boot/board/isee/igep00x0/Kconfig | 14 | ||||
| -rw-r--r-- | roms/u-boot/board/isee/igep00x0/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/isee/igep00x0/Makefile | 10 | ||||
| -rw-r--r-- | roms/u-boot/board/isee/igep00x0/common.c | 69 | ||||
| -rw-r--r-- | roms/u-boot/board/isee/igep00x0/igep00x0.c | 263 | ||||
| -rw-r--r-- | roms/u-boot/board/isee/igep00x0/igep00x0.h | 127 | ||||
| -rw-r--r-- | roms/u-boot/board/isee/igep00x0/spl.c | 64 |
7 files changed, 553 insertions, 0 deletions
diff --git a/roms/u-boot/board/isee/igep00x0/Kconfig b/roms/u-boot/board/isee/igep00x0/Kconfig new file mode 100644 index 000000000..597d6d92c --- /dev/null +++ b/roms/u-boot/board/isee/igep00x0/Kconfig @@ -0,0 +1,14 @@ +if TARGET_OMAP3_IGEP00X0 + +config SYS_BOARD + default "igep00x0" + +config SYS_VENDOR + default "isee" + +config SYS_CONFIG_NAME + default "omap3_igep00x0" + +source "board/ti/common/Kconfig" + +endif diff --git a/roms/u-boot/board/isee/igep00x0/MAINTAINERS b/roms/u-boot/board/isee/igep00x0/MAINTAINERS new file mode 100644 index 000000000..a07c9f49a --- /dev/null +++ b/roms/u-boot/board/isee/igep00x0/MAINTAINERS @@ -0,0 +1,6 @@ +IGEP00X0 BOARD +M: Enric Balletbo i Serra <eballetbo@gmail.com> +S: Maintained +F: board/isee/igep00x0/ +F: include/configs/omap3_igep00x0.h +F: configs/igep00x0_defconfig diff --git a/roms/u-boot/board/isee/igep00x0/Makefile b/roms/u-boot/board/isee/igep00x0/Makefile new file mode 100644 index 000000000..e095bcada --- /dev/null +++ b/roms/u-boot/board/isee/igep00x0/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +ifdef CONFIG_SPL_BUILD +obj-y := spl.o common.o +else +obj-y := igep00x0.o common.o +endif diff --git a/roms/u-boot/board/isee/igep00x0/common.c b/roms/u-boot/board/isee/igep00x0/common.c new file mode 100644 index 000000000..3fdf83e84 --- /dev/null +++ b/roms/u-boot/board/isee/igep00x0/common.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <twl4030.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/omap_mmc.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/delay.h> +#include <linux/mtd/rawnand.h> +#include "igep00x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + int loops = 100; + + /* find out flash memory type, assume NAND first */ + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + gpmc_init(); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + udelay(1); + if (--loops == 0) { + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + gpmc_init(); /* reinitialize for OneNAND */ + break; + } + } + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#if defined(CONFIG_MMC) +int board_mmc_init(struct bd_info *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/roms/u-boot/board/isee/igep00x0/igep00x0.c b/roms/u-boot/board/isee/igep00x0/igep00x0.c new file mode 100644 index 000000000..0932f62b9 --- /dev/null +++ b/roms/u-boot/board/isee/igep00x0/igep00x0.c @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010 + * ISEE 2007 SL, <www.iseebcn.com> + */ +#include <common.h> +#include <env.h> +#include <init.h> +#include <malloc.h> +#include <net.h> +#include <status_led.h> +#include <dm.h> +#include <ns16550.h> +#include <twl4030.h> +#include <netdev.h> +#include <spl.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/rawnand.h> +#include <linux/mtd/onenand.h> +#include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <fdt_support.h> +#include "igep00x0.h" + +static const struct ns16550_plat igep_serial = { + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, +}; + +U_BOOT_DRVINFO(igep_uart) = { + "ns16550_serial", + &igep_serial +}; + +/* + * Routine: get_board_revision + * Description: GPIO_28 and GPIO_129 are used to read board and revision from + * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from + * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because + * this functionality is shared by USB HOST. + * Once USB reset is applied, U-boot configures these pins as input pullup to + * detect board and revision: + * IGEP0020-RF = 0b00 + * IGEP0020-RC = 0b01 + * IGEP0030-RG = 0b10 + * IGEP0030-RE = 0b11 + */ +static int get_board_revision(void) +{ + int revision; + + gpio_request(IGEP0030_USB_TRANSCEIVER_RESET, + "igep0030_usb_transceiver_reset"); + gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0); + + gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection"); + gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION); + revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION); + gpio_free(GPIO_IGEP00X0_BOARD_DETECTION); + + gpio_request(GPIO_IGEP00X0_REVISION_DETECTION, + "igep00x0_revision_detection"); + gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION); + revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION); + gpio_free(GPIO_IGEP00X0_REVISION_DETECTION); + + gpio_free(IGEP0030_USB_TRANSCEIVER_RESET); + + return revision; +} + +int onenand_board_init(struct mtd_info *mtd) +{ + if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { + struct onenand_chip *this = mtd->priv; + this->base = (void *)CONFIG_SYS_ONENAND_BASE; + return 0; + } + return 1; +} + +#if defined(CONFIG_CMD_NET) +static void reset_net_chip(int gpio) +{ + if (!gpio_request(gpio, "eth nrst")) { + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + udelay(40); + gpio_set_value(gpio, 1); + mdelay(10); + } +} + +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + }; + + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + reset_net_chip(64); +} + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_SMC911X + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; +#endif +} +#else +static inline void setup_net_chip(void) {} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +static int ft_enable_by_compatible(void *blob, char *compat, int enable) +{ + int off = fdt_node_offset_by_compatible(blob, -1, compat); + if (off < 0) + return off; + + if (enable) + fdt_status_okay(blob, off); + else + fdt_status_disabled(blob, off); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + static const struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, + { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, }, + }; + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + ft_enable_by_compatible(blob, "ti,omap2-nand", + gpmc_cs0_flash == MTD_DEV_TYPE_NAND); + ft_enable_by_compatible(blob, "ti,omap2-onenand", + gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND); + + return 0; +} +#endif + +void set_led(void) +{ + switch (get_board_revision()) { + case 0: + case 1: + gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led"); + gpio_direction_output(IGEP0020_GPIO_LED, 1); + break; + case 2: + case 3: + gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led"); + gpio_direction_output(IGEP0030_GPIO_LED, 0); + break; + default: + /* Should not happen... */ + break; + } +} + +void set_boardname(void) +{ + char rev[5] = { 'F','C','G','E', }; + int i = get_board_revision(); + + rev[i+1] = 0; + env_set("board_rev", rev + i); + env_set("board_name", i < 2 ? "igep0020" : "igep0030"); +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + t2_t *t2_base = (t2_t *)T2_BASE; + u32 pbias_lite; + + twl4030_power_init(); + + /* set VSIM to 1.8V */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED, + TWL4030_PM_RECEIVER_VSIM_VSEL_18, + TWL4030_PM_RECEIVER_VSIM_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + /* set up dual-voltage GPIOs to 1.8V */ + pbias_lite = readl(&t2_base->pbias_lite); + pbias_lite &= ~PBIASLITEVMODE1; + pbias_lite |= PBIASLITEPWRDNZ1; + writel(pbias_lite, &t2_base->pbias_lite); + if (get_cpu_family() == CPU_OMAP36XX) + writel(readl(OMAP34XX_CTRL_WKUP_CTRL) | + OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, + OMAP34XX_CTRL_WKUP_CTRL); + + setup_net_chip(); + + omap_die_id_display(); + + set_led(); + + set_boardname(); + + return 0; +} + +void board_mtdparts_default(const char **mtdids, const char **mtdparts) +{ + struct mtd_info *mtd = get_mtd_device(NULL, 0); + if (mtd) { + static char ids[24]; + static char parts[48]; + const char *linux_name = "omap2-nand"; + if (strncmp(mtd->name, "onenand0", 8) == 0) + linux_name = "omap2-onenand"; + snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name); + snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)", + linux_name, 4 * mtd->erasesize >> 10); + *mtdids = ids; + *mtdparts = parts; + } +} diff --git a/roms/u-boot/board/isee/igep00x0/igep00x0.h b/roms/u-boot/board/isee/igep00x0/igep00x0.h new file mode 100644 index 000000000..aa532acad --- /dev/null +++ b/roms/u-boot/board/isee/igep00x0/igep00x0.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * ISEE 2007 SL, <www.iseebcn.com> + */ +#ifndef _IGEP00X0_H_ +#define _IGEP00X0_H_ + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\ + MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ +#endif diff --git a/roms/u-boot/board/isee/igep00x0/spl.c b/roms/u-boot/board/isee/igep00x0/spl.c new file mode 100644 index 000000000..f814fe135 --- /dev/null +++ b/roms/u-boot/board/isee/igep00x0/spl.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <serial.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/rawnand.h> +#include "igep00x0.h" + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + int mfr, id, err = identify_nand_chip(&mfr, &id); + + timings->mr = MICRON_V_MR_165; + if (!err) { + switch (mfr) { + case NAND_MFR_HYNIX: + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + break; + case NAND_MFR_MICRON: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + break; + default: + /* Should not happen... */ + break; + } + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + } else { + if (get_cpu_family() == CPU_OMAP34XX) { + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + } +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif |