diff options
Diffstat (limited to 'roms/u-boot/board/logicpd/omap3som')
| -rw-r--r-- | roms/u-boot/board/logicpd/omap3som/Kconfig | 14 | ||||
| -rw-r--r-- | roms/u-boot/board/logicpd/omap3som/MAINTAINERS | 9 | ||||
| -rw-r--r-- | roms/u-boot/board/logicpd/omap3som/Makefile | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/logicpd/omap3som/README | 56 | ||||
| -rw-r--r-- | roms/u-boot/board/logicpd/omap3som/omap3logic.c | 241 | ||||
| -rw-r--r-- | roms/u-boot/board/logicpd/omap3som/omap3logic.h | 255 |
6 files changed, 581 insertions, 0 deletions
diff --git a/roms/u-boot/board/logicpd/omap3som/Kconfig b/roms/u-boot/board/logicpd/omap3som/Kconfig new file mode 100644 index 000000000..68d40dcd6 --- /dev/null +++ b/roms/u-boot/board/logicpd/omap3som/Kconfig @@ -0,0 +1,14 @@ +if TARGET_OMAP3_LOGIC + +config SYS_BOARD + default "omap3som" + +config SYS_VENDOR + default "logicpd" + +config SYS_CONFIG_NAME + default "omap3_logic" + +source "board/ti/common/Kconfig" + +endif diff --git a/roms/u-boot/board/logicpd/omap3som/MAINTAINERS b/roms/u-boot/board/logicpd/omap3som/MAINTAINERS new file mode 100644 index 000000000..459393cf5 --- /dev/null +++ b/roms/u-boot/board/logicpd/omap3som/MAINTAINERS @@ -0,0 +1,9 @@ +OMAP3SOM BOARD +M: Adam Ford <aford173@gmail.com> +S: Maintained +F: board/logicpd/omap3som/ +F: include/configs/omap3_logic.h +F: configs/omap3_logic_defconfig +F: configs/omap35_logic_defconfig +F: configs/omap35_logic_somlv_defconfig +F: configs/omap3_logic_somlv_defconfig diff --git a/roms/u-boot/board/logicpd/omap3som/Makefile b/roms/u-boot/board/logicpd/omap3som/Makefile new file mode 100644 index 000000000..61ef14e87 --- /dev/null +++ b/roms/u-boot/board/logicpd/omap3som/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y := omap3logic.o diff --git a/roms/u-boot/board/logicpd/omap3som/README b/roms/u-boot/board/logicpd/omap3som/README new file mode 100644 index 000000000..5aaf58f0a --- /dev/null +++ b/roms/u-boot/board/logicpd/omap3som/README @@ -0,0 +1,56 @@ +Summary +======= + +The source for omap3logic.c encompases the OMAP35 and DM3730 SOM-LV and DM3730 Torpedo platforms, but there are device trees custom taylored to each board. + +omap3_logic_defconfig = DM37 Torpedo / Torpedo + Wireless +omap35_logic_defconfig = OMAP35 Torpedo +omap3_logic_somlv_defconfig = DM37 SOM-LV +omap35_logic_somlv_defconfig = OMAP35 SOM-LV + +The device tree included with each of the defconfig files will also direct the board as to which dtb file to load when loading the kernel, so it is not +recomended to mix and match the defconfig files. + +Falcon Mode: FAT SD cards +========================= + +In this case the additional file is written to the filesystem. In this +example we assume that the uImage and device tree to be used are already on +the FAT filesystem (only the uImage MUST be for this to function +afterwards) along with a Falcon Mode aware MLO and the FAT partition has +already been created and marked bootable: + +U-Boot # mmc rescan +# Load kernel and device tree into memory, perform export +U-Boot # fatload mmc 0 ${loadaddr} uImage +U-Boot # run loadfdt +U-Boot # setenv optargs quiet +U-Boot # run mmcargs +U-Boot # run common_bootargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} + +This will print a number of lines and then end with something like: + Loading Device Tree to 8dec9000, end 8dee0295 ... OK + +So then note the starting address and write the args to mmc/sd: + +U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000 + +The size of 0x20000 matches the CMD_SPL_WRITE_SIZE. + +Falcon Mode: NAND +================= + +In this case the additional data is written to another partition of the +NAND. In this example we assume that the uImage and device tree to be are +already located on the NAND somewhere (such as filesystem or mtd partition) +along with a Falcon Mode aware MLO written to the correct locations for +booting and mtdparts have been configured correctly for the board: + +U-Boot # nand read ${loadaddr} kernel +U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb +U-Boot # run nandargs +U-Boot # run common_bootargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} +U-Boot # nand erase.part u-boot-spl-os +U-Boot # nand write ${fdtaddr} u-boot-spl-os diff --git a/roms/u-boot/board/logicpd/omap3som/omap3logic.c b/roms/u-boot/board/logicpd/omap3som/omap3logic.c new file mode 100644 index 000000000..2379b5219 --- /dev/null +++ b/roms/u-boot/board/logicpd/omap3som/omap3logic.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2011 + * Logic Product Development <www.logicpd.com> + * + * Author : + * Peter Barada <peter.barada@logicpd.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + */ +#include <common.h> +#include <dm.h> +#include <init.h> +#include <net.h> +#include <ns16550.h> +#include <flash.h> +#include <nand.h> +#include <i2c.h> +#include <serial.h> +#include <twl4030.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/omap_mmc.h> +#include <asm/mach-types.h> +#include <linux/mtd/rawnand.h> +#include <asm/omap_musb.h> +#include <linux/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> +#include "omap3logic.h" +#ifdef CONFIG_USB_EHCI_HCD +#include <usb.h> +#include <asm/ehci-omap.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50 + +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50 + +#define CONFIG_SMC911X_BASE 0x08000000 + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#if defined(CONFIG_SPL_BUILD) +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->mr = MICRON_V_MR_165; + + if (get_cpu_family() == CPU_OMAP36XX) { + /* 200 MHz works for OMAP36/DM37 */ + /* 256MB DDR */ + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + /* 165 MHz works for OMAP35 */ + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} + +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80) + +void spl_board_prepare_for_linux(void) +{ + /* The Micron NAND starts locked which + * prohibits mounting the NAND as RW + * The following commands are what unlocks + * the NAND to become RW Falcon Mode does not + * have as many smarts as U-Boot, but Logic PD + * only makes NAND with 512MB so these hard coded + * values should work for all current models + */ + + writeb(0x70, GPMC_NAND_COMMAND_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(0x7a, GPMC_NAND_COMMAND_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_COMMAND_0); + + /* Begin address 0 */ + writeb(NAND_CMD_UNLOCK1, 0x6e00007c); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_DATA_0); + + /* Ending address at the end of Flash */ + writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0); + writeb(0xc0, GPMC_NAND_ADDRESS_0); + writeb(0xff, GPMC_NAND_ADDRESS_0); + writeb(0x03, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(0x79, GPMC_NAND_COMMAND_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(-1, GPMC_NAND_DATA_0); +} +#endif + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + twl4030_power_init(); + twl4030_power_mmc_init(0); + omap_die_id_display(); + return 0; +} + +#if defined(CONFIG_FLASH_CFI_DRIVER) +static const u32 gpmc_dm37_c2nor_config[] = { + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 +}; + +static const u32 gpmc_omap35_c2nor_config[] = { + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 +}; +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); +#if defined(CONFIG_FLASH_CFI_DRIVER) + if (get_cpu_family() == CPU_OMAP36XX) { + /* Enable CS2 for NOR Flash */ + enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } else { + enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } +#endif + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT + +static void unlock_nand(void) +{ + int dev = nand_curr_device; + struct mtd_info *mtd; + + mtd = get_nand_dev_by_index(dev); + nand_unlock(mtd, 0, mtd->size, 0); +} + +#ifdef CONFIG_SMC911X +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ +static const u32 gpmc_lan92xx_config[] = { + NET_LAN92XX_GPMC_CONFIG1, + NET_LAN92XX_GPMC_CONFIG2, + NET_LAN92XX_GPMC_CONFIG3, + NET_LAN92XX_GPMC_CONFIG4, + NET_LAN92XX_GPMC_CONFIG5, + NET_LAN92XX_GPMC_CONFIG6, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK + unlock_nand(); +#endif + +#ifdef CONFIG_SMC911X + enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); +#endif + return 0; +} +#endif + +#if defined(CONFIG_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/roms/u-boot/board/logicpd/omap3som/omap3logic.h b/roms/u-boot/board/logicpd/omap3som/omap3logic.h new file mode 100644 index 000000000..63c214178 --- /dev/null +++ b/roms/u-boot/board/logicpd/omap3som/omap3logic.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Logic Product Development <www.logicpd.com> + * + * Author: + * Peter Barada <peter.barada@logicpd.com> + */ +#ifndef _OMAP3LOGIC_H_ +#define _OMAP3LOGIC_H_ + +/* + * OMAP3 GPMC register settings for CS1 LAN922x + */ +#define NET_LAN92XX_GPMC_CONFIG1 0x00001000 +#define NET_LAN92XX_GPMC_CONFIG2 0x00080801 +#define NET_LAN92XX_GPMC_CONFIG3 0x00000000 +#define NET_LAN92XX_GPMC_CONFIG4 0x08010801 +#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a +#define NET_LAN92XX_GPMC_CONFIG6 0x03000280 + + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "Logic DM37x/OMAP35x reference board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ + + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/ + + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ + + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/ + + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/ + + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/ +#ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/ +#endif + + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/ + +#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/ +#endif + +} + +#endif |