diff options
Diffstat (limited to 'roms/u-boot/board/qca')
| -rw-r--r-- | roms/u-boot/board/qca/ap121/Kconfig | 27 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap121/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap121/Makefile | 3 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap121/ap121.c | 47 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap143/Kconfig | 27 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap143/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap143/Makefile | 3 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap143/ap143.c | 63 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap152/Kconfig | 15 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap152/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap152/Makefile | 3 | ||||
| -rw-r--r-- | roms/u-boot/board/qca/ap152/ap152.c | 82 |
12 files changed, 288 insertions, 0 deletions
diff --git a/roms/u-boot/board/qca/ap121/Kconfig b/roms/u-boot/board/qca/ap121/Kconfig new file mode 100644 index 000000000..4fd6a7167 --- /dev/null +++ b/roms/u-boot/board/qca/ap121/Kconfig @@ -0,0 +1,27 @@ +if TARGET_AP121 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap121" + +config SYS_CONFIG_NAME + default "ap121" + +config SYS_TEXT_BASE + default 0x9f000000 + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_ICACHE_LINE_SIZE + default 32 + +endif diff --git a/roms/u-boot/board/qca/ap121/MAINTAINERS b/roms/u-boot/board/qca/ap121/MAINTAINERS new file mode 100644 index 000000000..8b02988d6 --- /dev/null +++ b/roms/u-boot/board/qca/ap121/MAINTAINERS @@ -0,0 +1,6 @@ +AP121 BOARD +M: Wills Wang <wills.wang@live.com> +S: Maintained +F: board/qca/ap121/ +F: include/configs/ap121.h +F: configs/ap121_defconfig diff --git a/roms/u-boot/board/qca/ap121/Makefile b/roms/u-boot/board/qca/ap121/Makefile new file mode 100644 index 000000000..7cdf53cf9 --- /dev/null +++ b/roms/u-boot/board/qca/ap121/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y = ap121.o diff --git a/roms/u-boot/board/qca/ap121/ap121.c b/roms/u-boot/board/qca/ap121/ap121.c new file mode 100644 index 000000000..60a2e1914 --- /dev/null +++ b/roms/u-boot/board/qca/ap121/ap121.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <mach/ath79.h> +#include <debug_uart.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val &= ~AR933X_GPIO(9); + val |= AR933X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO + */ + val = readl(regs + AR71XX_GPIO_REG_FUNC); + val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE; + writel(val, regs + AR71XX_GPIO_REG_FUNC); +} +#endif + +int board_early_init_f(void) +{ + ddr_init(); + ath79_eth_reset(); + return 0; +} diff --git a/roms/u-boot/board/qca/ap143/Kconfig b/roms/u-boot/board/qca/ap143/Kconfig new file mode 100644 index 000000000..74c632a03 --- /dev/null +++ b/roms/u-boot/board/qca/ap143/Kconfig @@ -0,0 +1,27 @@ +if TARGET_AP143 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap143" + +config SYS_CONFIG_NAME + default "ap143" + +config SYS_TEXT_BASE + default 0x9f000000 + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_ICACHE_LINE_SIZE + default 32 + +endif diff --git a/roms/u-boot/board/qca/ap143/MAINTAINERS b/roms/u-boot/board/qca/ap143/MAINTAINERS new file mode 100644 index 000000000..11cb14fc7 --- /dev/null +++ b/roms/u-boot/board/qca/ap143/MAINTAINERS @@ -0,0 +1,6 @@ +AP143 BOARD +M: Wills Wang <wills.wang@live.com> +S: Maintained +F: board/qca/ap143/ +F: include/configs/ap143.h +F: configs/ap143_defconfig diff --git a/roms/u-boot/board/qca/ap143/Makefile b/roms/u-boot/board/qca/ap143/Makefile new file mode 100644 index 000000000..bf9fd83af --- /dev/null +++ b/roms/u-boot/board/qca/ap143/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y = ap143.o diff --git a/roms/u-boot/board/qca/ap143/ap143.c b/roms/u-boot/board/qca/ap143/ap143.c new file mode 100644 index 000000000..ac6505413 --- /dev/null +++ b/roms/u-boot/board/qca/ap143/ap143.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <mach/ath79.h> +#include <debug_uart.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val |= QCA953X_GPIO(9); + val &= ~QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable GPIO10 as UART0_SOUT + */ + val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); + val &= ~QCA953X_GPIO_MUX_MASK(16); + val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; + writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); + + /* + * Enable GPIO9 as UART0_SIN + */ + val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); + val &= ~QCA953X_GPIO_MUX_MASK(8); + val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; + writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); + + /* + * Enable GPIO10 output + */ + val = readl(regs + AR71XX_GPIO_REG_OUT); + val |= QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OUT); +} +#endif + +int board_early_init_f(void) +{ + ddr_init(); + ath79_eth_reset(); + return 0; +} diff --git a/roms/u-boot/board/qca/ap152/Kconfig b/roms/u-boot/board/qca/ap152/Kconfig new file mode 100644 index 000000000..f6ad498e8 --- /dev/null +++ b/roms/u-boot/board/qca/ap152/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AP152 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap152" + +config SYS_CONFIG_NAME + default "ap152" + +config SYS_TEXT_BASE + default 0x9f000000 + +endif diff --git a/roms/u-boot/board/qca/ap152/MAINTAINERS b/roms/u-boot/board/qca/ap152/MAINTAINERS new file mode 100644 index 000000000..785ec2766 --- /dev/null +++ b/roms/u-boot/board/qca/ap152/MAINTAINERS @@ -0,0 +1,6 @@ +AP152 BOARD +M: Rosy Song <rosysong@rosinson.com> +S: Maintained +F: board/qca/ap152/ +F: include/configs/ap152.h +F: configs/ap152_defconfig diff --git a/roms/u-boot/board/qca/ap152/Makefile b/roms/u-boot/board/qca/ap152/Makefile new file mode 100644 index 000000000..4270afa12 --- /dev/null +++ b/roms/u-boot/board/qca/ap152/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y = ap152.o diff --git a/roms/u-boot/board/qca/ap152/ap152.c b/roms/u-boot/board/qca/ap152/ap152.c new file mode 100644 index 000000000..1064705d2 --- /dev/null +++ b/roms/u-boot/board/qca/ap152/ap152.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <mach/ath79.h> +#include <debug_uart.h> + +#define RST_RESET_RTC_RESET_LSB 27 +#define RST_RESET_RTC_RESET_MASK 0x08000000 +#define RST_RESET_RTC_RESET_SET(x) \ + (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK) + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* UART : RX18, TX22 done + * GPIO18 as input, GPIO22 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val |= QCA956X_GPIO(18); + val &= ~QCA956X_GPIO(22); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable GPIO22 as UART0_SOUT + */ + val = readl(regs + QCA956X_GPIO_REG_OUT_FUNC5); + val &= ~QCA956X_GPIO_MUX_MASK(16); + val |= QCA956X_GPIO_OUT_MUX_UART0_SOUT << 16; + writel(val, regs + QCA956X_GPIO_REG_OUT_FUNC5); + + /* + * Enable GPIO18 as UART0_SIN + */ + val = readl(regs + QCA956X_GPIO_REG_IN_ENABLE0); + val &= ~QCA956X_GPIO_MUX_MASK(8); + val |= QCA956X_GPIO_IN_MUX_UART0_SIN << 8; + writel(val, regs + QCA956X_GPIO_REG_IN_ENABLE0); + + /* + * Enable GPIO22 output + */ + val = readl(regs + AR71XX_GPIO_REG_OUT); + val |= QCA956X_GPIO(22); + writel(val, regs + AR71XX_GPIO_REG_OUT); +} +#endif + +int board_early_init_f(void) +{ + u32 reg; + void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE, MAP_NOCACHE); + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CPU:775, DDR:650, AHB:258 */ + qca956x_pll_init(); + qca956x_ddr_init(); +#endif + + /* Take WMAC out of reset */ + reg = readl(rst_regs + QCA956X_RESET_REG_RESET_MODULE); + reg &= (~RST_RESET_RTC_RESET_SET(1)); + writel(reg, rst_regs + QCA956X_RESET_REG_RESET_MODULE); + + ath79_eth_reset(); + return 0; +} |