5 files changed, 317 insertions, 0 deletions
diff --git a/roms/u-boot/board/renesas/ulcb/Kconfig b/roms/u-boot/board/renesas/ulcb/Kconfig
new file mode 100644
index 000000000..1e9a10d28
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ULCB
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "ulcb"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "ulcb"
+
+endif
diff --git a/roms/u-boot/board/renesas/ulcb/MAINTAINERS b/roms/u-boot/board/renesas/ulcb/MAINTAINERS
new file mode 100644
index 000000000..564eb561b
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/MAINTAINERS
@@ -0,0 +1,6 @@
+ULCB BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/ulcb/
+F:	include/configs/ulcb.h
+F:	configs/rcar3_ulcb_defconfig
diff --git a/roms/u-boot/board/renesas/ulcb/Makefile b/roms/u-boot/board/renesas/ulcb/Makefile
new file mode 100644
index 000000000..f4d24c68a
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/ulcb/Makefile
+#
+# Copyright (C) 2017 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= ulcb.o cpld.o ../rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/renesas/ulcb/cpld.c b/roms/u-boot/board/renesas/ulcb/cpld.c
new file mode 100644
index 000000000..ebb2d6f74
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/cpld.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ULCB board CPLD access support
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <sysreset.h>
+
+#define CPLD_ADDR_MODE		0x00 /* RW */
+#define CPLD_ADDR_MUX		0x02 /* RW */
+#define CPLD_ADDR_DIPSW6	0x08 /* R */
+#define CPLD_ADDR_RESET		0x80 /* RW */
+#define CPLD_ADDR_VERSION	0xFF /* R */
+
+struct renesas_ulcb_sysreset_priv {
+	struct gpio_desc	miso;
+	struct gpio_desc	mosi;
+	struct gpio_desc	sck;
+	struct gpio_desc	sstbz;
+};
+
+static u32 cpld_read(struct udevice *dev, u8 addr)
+{
+	struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+	u32 data = 0;
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 1);
+		addr <<= 1;
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	dm_gpio_set_value(&priv->mosi, 0); /* READ */
+	dm_gpio_set_value(&priv->sstbz, 0);
+	dm_gpio_set_value(&priv->sck, 1);
+	dm_gpio_set_value(&priv->sck, 0);
+	dm_gpio_set_value(&priv->sstbz, 1);
+
+	for (i = 0; i < 32; i++) {
+		dm_gpio_set_value(&priv->sck, 1);
+		data <<= 1;
+		data |= dm_gpio_get_value(&priv->miso); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	return data;
+}
+
+static void cpld_write(struct udevice *dev, u8 addr, u32 data)
+{
+	struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+	int i;
+
+	for (i = 0; i < 32; i++) {
+		dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 1);
+		data <<= 1;
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	for (i = 0; i < 8; i++) {
+		dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 1);
+		addr <<= 1;
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
+	dm_gpio_set_value(&priv->sstbz, 0);
+	dm_gpio_set_value(&priv->sck, 1);
+	dm_gpio_set_value(&priv->sck, 0);
+	dm_gpio_set_value(&priv->sstbz, 1);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	struct udevice *dev;
+	u32 addr, val;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+					  DM_DRIVER_GET(sysreset_renesas_ulcb),
+					  &dev);
+	if (ret)
+		return ret;
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("CPLD version:\t\t\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_VERSION));
+		printf("H3 Mode setting (MD0..28):\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_MODE));
+		printf("Multiplexer settings:\t\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_MUX));
+		printf("DIPSW (SW6):\t\t\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_DIPSW6));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
+	      addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
+	      addr == CPLD_ADDR_RESET)) {
+		printf("Invalid CPLD register address\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(dev, addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(dev, addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cpld, 4, 1, do_cpld,
+	"CPLD access",
+	"info\n"
+	"cpld read addr\n"
+	"cpld write addr val\n"
+);
+
+static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+	return -EINPROGRESS;
+}
+
+static int renesas_ulcb_sysreset_probe(struct udevice *dev)
+{
+	struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+
+	if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
+				 GPIOD_IS_IN))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
+				 GPIOD_IS_OUT))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
+				 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
+				 GPIOD_IS_OUT))
+		return -EINVAL;
+
+	/* PULL-UP on MISO line */
+	setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
+
+	/* Dummy read */
+	cpld_read(dev, CPLD_ADDR_VERSION);
+
+	return 0;
+}
+
+static struct sysreset_ops renesas_ulcb_sysreset = {
+	.request	= renesas_ulcb_sysreset_request,
+};
+
+static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
+	{ .compatible = "renesas,ulcb-cpld" },
+	{ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
+	.name		= "renesas_ulcb_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.ops		= &renesas_ulcb_sysreset,
+	.probe		= renesas_ulcb_sysreset_probe,
+	.of_match	= renesas_ulcb_sysreset_ids,
+	.priv_auto	= sizeof(struct renesas_ulcb_sysreset_priv),
+};
diff --git a/roms/u-boot/board/renesas/ulcb/ulcb.c b/roms/u-boot/board/renesas/ulcb/ulcb.c
new file mode 100644
index 000000000..7ba194865
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/ulcb.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/ulcb/ulcb.c
+ *     This file is ULCB board support.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DVFS_MSTP926		BIT(26)
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+	return 0;
+}
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+	return 0;
+}
+
+#ifdef CONFIG_MULTI_DTB_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* PRR driver is not available yet */
+	u32 cpu_type = rmobile_get_cpu_type();
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
+	    !strcmp(name, "r8a77950-ulcb-u-boot"))
+		return 0;
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
+	    !strcmp(name, "r8a77960-ulcb-u-boot"))
+		return 0;
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
+	    !strcmp(name, "r8a77965-ulcb-u-boot"))
+		return 0;
+
+	return -1;
+}
+#endif