diff options
Diffstat (limited to 'roms/u-boot/board/socrates')
| -rw-r--r-- | roms/u-boot/board/socrates/Kconfig | 9 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/MAINTAINERS | 8 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/Makefile | 13 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/ddr.c | 53 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/law.c | 41 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/nand.c | 162 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/sdram.c | 97 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/socrates.c | 242 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/tlb.c | 104 | ||||
| -rw-r--r-- | roms/u-boot/board/socrates/upm_table.h | 58 |
10 files changed, 787 insertions, 0 deletions
diff --git a/roms/u-boot/board/socrates/Kconfig b/roms/u-boot/board/socrates/Kconfig new file mode 100644 index 000000000..ca945c278 --- /dev/null +++ b/roms/u-boot/board/socrates/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SOCRATES + +config SYS_BOARD + default "socrates" + +config SYS_CONFIG_NAME + default "socrates" + +endif diff --git a/roms/u-boot/board/socrates/MAINTAINERS b/roms/u-boot/board/socrates/MAINTAINERS new file mode 100644 index 000000000..2b27a73c1 --- /dev/null +++ b/roms/u-boot/board/socrates/MAINTAINERS @@ -0,0 +1,8 @@ +SOCRATES BOARD +M: Heiko Schocher <hs@denx.de> +S: Maintained +F: board/socrates/ +F: include/configs/socrates.h +F: configs/socrates_defconfig +F: arch/powerpc/dts/socrates.dts +F: arch/powerpc/dts/socrates-u-boot.dtsi diff --git a/roms/u-boot/board/socrates/Makefile b/roms/u-boot/board/socrates/Makefile new file mode 100644 index 000000000..e14db8e5d --- /dev/null +++ b/roms/u-boot/board/socrates/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2008 +# Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += socrates.o +obj-y += law.o +obj-y += tlb.o +obj-y += nand.o +obj-y += sdram.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/roms/u-boot/board/socrates/ddr.c b/roms/u-boot/board/socrates/ddr.c new file mode 100644 index 000000000..3a94f7bec --- /dev/null +++ b/roms/u-boot/board/socrates/ddr.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2008 Freescale Semiconductor, Inc. + */ + +#include <common.h> + +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/roms/u-boot/board/socrates/law.c b/roms/u-boot/board/socrates/law.c new file mode 100644 index 000000000..840941b63 --- /dev/null +++ b/roms/u-boot/board/socrates/law.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x2fff_ffff DDR 512M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xc00f_ffff FPGA 1M + * 0xc800_0000 0xcbff_ffff LIME 64M + * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xfc00_0000 0xffff_ffff FLASH 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#if defined(CONFIG_SYS_FPGA_BASE) + SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif + SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/roms/u-boot/board/socrates/nand.c b/roms/u-boot/board/socrates/nand.c new file mode 100644 index 000000000..07c493679 --- /dev/null +++ b/roms/u-boot/board/socrates/nand.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + */ + +#include <common.h> + +#if defined(CONFIG_SYS_NAND_BASE) +#include <nand.h> +#include <linux/errno.h> +#include <asm/io.h> + +static int state; +static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte); +static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); +static u_char sc_nand_read_byte(struct mtd_info *mtd); +static u16 sc_nand_read_word(struct mtd_info *mtd); +static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +static int sc_nand_device_ready(struct mtd_info *mtdinfo); + +#define FPGA_NAND_CMD_MASK (0x7 << 28) +#define FPGA_NAND_CMD_COMMAND (0x0 << 28) +#define FPGA_NAND_CMD_ADDR (0x1 << 28) +#define FPGA_NAND_CMD_READ (0x2 << 28) +#define FPGA_NAND_CMD_WRITE (0x3 << 28) +#define FPGA_NAND_BUSY (0x1 << 15) +#define FPGA_NAND_ENABLE (0x1 << 31) +#define FPGA_NAND_DATA_SHIFT 16 + +/** + * sc_nand_write_byte - write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + */ +static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); +} + +/** + * sc_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd_to_nand(mtd); + + for (i = 0; i < len; i++) { + out_be32(this->IO_ADDR_W, + state | (buf[i] << FPGA_NAND_DATA_SHIFT)); + } +} + + +/** + * sc_nand_read_byte - read one byte from the chip + * @mtd: MTD device structure + */ +static u_char sc_nand_read_byte(struct mtd_info *mtd) +{ + u8 byte; + sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); + return byte; +} + +/** + * sc_nand_read_word - read one word from the chip + * @mtd: MTD device structure + */ +static u16 sc_nand_read_word(struct mtd_info *mtd) +{ + u16 word; + sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); + return word; +} + +/** + * sc_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd_to_nand(mtd); + int val; + + val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; + + out_be32(this->IO_ADDR_W, val); + for (i = 0; i < len; i++) { + buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff; + } +} + +/** + * sc_nand_device_ready - Check the NAND device is ready for next command. + * @mtd: MTD device structure + */ +static int sc_nand_device_ready(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtd_to_nand(mtdinfo); + + if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) + return 0; /* busy */ + return 1; +} + +/** + * sc_nand_hwcontrol - NAND control functions wrapper. + * @mtd: MTD device structure + * @cmd: Command + */ +static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE); + + switch (ctrl & (NAND_ALE | NAND_CLE)) { + case 0: + state |= FPGA_NAND_CMD_WRITE; + break; + + case NAND_ALE: + state |= FPGA_NAND_CMD_ADDR; + break; + + case NAND_CLE: + state |= FPGA_NAND_CMD_COMMAND; + break; + + default: + printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl); + } + + if (ctrl & NAND_NCE) + state |= FPGA_NAND_ENABLE; + } + + if (cmd != NAND_CMD_NONE) + sc_nand_write_byte(mtdinfo, cmd); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->cmd_ctrl = sc_nand_hwcontrol; + nand->ecc.mode = NAND_ECC_SOFT; + nand->dev_ready = sc_nand_device_ready; + nand->read_byte = sc_nand_read_byte; + nand->read_word = sc_nand_read_word; + nand->write_buf = sc_nand_write_buf; + nand->read_buf = sc_nand_read_buf; + + return 0; +} + +#endif diff --git a/roms/u-boot/board/socrates/sdram.c b/roms/u-boot/board/socrates/sdram.c new file mode 100644 index 000000000..d358a209a --- /dev/null +++ b/roms/u-boot/board/socrates/sdram.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + */ + +#include <common.h> +#include <init.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <fsl_ddr_sdram.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <spd_sdram.h> +#include <linux/delay.h> + + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Autodetect onboard DDR SDRAM on 85xx platforms + * + * NOTE: Some of the hardcoded values are hardware dependant, + * so this should be extended for other future boards + * using this routine! + */ +phys_size_t fixed_sdram(void) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + + /* + * Disable memory controller. + */ + ddr->cs0_config = 0; + ddr->sdram_cfg = 0; + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; + + asm ("sync;isync;msync"); + udelay(1000); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; + asm ("sync; isync; msync"); + udelay(1000); + + if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { + /* + * OK, size detected -> all done + */ + return CONFIG_SYS_SDRAM_SIZE<<20; + } + + return 0; /* nothing found ! */ +} +#endif + +#if defined(CONFIG_SYS_DRAM_TEST) +int testdram(void) +{ + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; + uint *p; + + printf ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test passed.\n"); + return 0; +} +#endif diff --git a/roms/u-boot/board/socrates/socrates.c b/roms/u-boot/board/socrates/socrates.c new file mode 100644 index 000000000..3444af6a8 --- /dev/null +++ b/roms/u-boot/board/socrates/socrates.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + */ + +#include <common.h> +#include <clock_legacy.h> +#include <env.h> +#include <init.h> +#include <pci.h> +#include <uuid.h> +#include <asm/global_data.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <ioports.h> +#include <flash.h> +#include <linux/delay.h> +#include <linux/libfdt.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <i2c.h> +#include <video_fb.h> +#include "upm_table.h" + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +void local_bus_init (void); +ulong flash_get_size (ulong base, int banknum); + +int checkboard (void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char buf[64]; + int f; + int i = env_get_f("serial#", buf, sizeof(buf)); +#ifdef CONFIG_PCI + char *src; +#endif + + puts("Board: Socrates"); + if (i > 0) { + puts(", serial# "); + puts(buf); + } + putc('\n'); + +#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI) + /* Check the PCI_clk sel bit */ + if (in_be32(&gur->porpllsr) & (1<<15)) { + src = "SYSCLK"; + f = CONFIG_SYS_CLK_FREQ; + } else { + src = "PCI_CLK"; + f = CONFIG_PCI_CLK_FREQ; + } + printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); +#else + printf ("PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init (); + return 0; +} + +int misc_init_r (void) +{ + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { + set_lbc_or(0, gd->bd->bi_flashstart | + (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); + set_lbc_br(0, gd->bd->bi_flashstart | + (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); + } + + /* + * Check if only one FLASH bank is available + */ + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { + set_lbc_or(1, 0); + set_lbc_br(1, 0); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect(FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + } + +#if defined(CONFIG_DM_PCI) + pci_init(); +#endif + + return 0; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + sys_info_t sysinfo; + uint clkdiv; + uint lbc_mhz; + uint lcrr = CONFIG_SYS_LBC_LCRR; + + get_sys_info (&sysinfo); + clkdiv = lbc->lcrr & LCRR_CLKDIV; + lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv; + + /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ + if (lbc_mhz >= 66) + lcrr &= ~LCRR_DBYP; /* DLL Enabled */ + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + + out_be32 (&lbc->lcrr, lcrr); + asm ("sync;isync;msync"); + + out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ + out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ + out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ + out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ + + /* Init UPMA for FPGA access */ + out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ + upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int)); + + /* Init UPMB for Lime controller access */ + out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ + upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int)); +} + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* set and reset the GPIO pin 2 which will reset the W83782G chip */ + out_8((unsigned char*)&gur->gpoutdr, 0x3F ); + out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ + udelay(200); + out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); + + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 val[12]; + int rc, i = 0; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR FLASH mapping */ + val[i++] = 0; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = gd->bd->bi_flashstart; + val[i++] = gd->bd->bi_flashsize; + + /* Fixup FPGA mapping */ + val[i++] = 3; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = CONFIG_SYS_FPGA_BASE; + val[i++] = CONFIG_SYS_FPGA_SIZE; + + rc = fdt_find_and_setprop(blob, "/localbus", "ranges", + val, i * sizeof(u32), 1); + if (rc) + printf("Unable to update localbus ranges, err=%s\n", + fdt_strerror(rc)); + + return 0; +} +#endif /* CONFIG_OF_BOARD_SETUP */ + +#if defined(CONFIG_OF_SEPARATE) +void *board_fdt_blob_setup(void) +{ + void *fw_dtb; + + fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE); + if (fdt_magic(fw_dtb) != FDT_MAGIC) { + printf("DTB is not passed via %x\n", (u32)fw_dtb); + return NULL; + } + + return fw_dtb; +} +#endif + +int get_serial_clock(void) +{ + return 333333330; +} diff --git a/roms/u-boot/board/socrates/tlb.c b/roms/u-boot/board/socrates/tlb.c new file mode 100644 index 000000000..de80c3c0e --- /dev/null +++ b/roms/u-boot/board/socrates/tlb.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + + /* + * TLB 1: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#if defined(CONFIG_SYS_FPGA_BASE) + /* + * TLB 4: 1M Non-cacheable, guarded + * 0xc0000000 1M FPGA and NAND + */ + SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1M, 1), +#endif + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xc8000000 16M LIME GDC framebuffer + * 0xc9fc0000 256K LIME GDC MMIO + * (0xcbfc0000 256K LIME GDC MMIO) + * MMIO is relocatable and could be at 0xcbfc0000 + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/roms/u-boot/board/socrates/upm_table.h b/roms/u-boot/board/socrates/upm_table.h new file mode 100644 index 000000000..1fc9c5c9a --- /dev/null +++ b/roms/u-boot/board/socrates/upm_table.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __UPM_TABLE_H +#define __UPM_TABLE_H + +/* UPM Table Configuration Code for FPGA access */ +static const unsigned int UPMTableA[] = +{ + 0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */ + 0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */ + 0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */ + 0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */ + 0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */ + 0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */ + 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */ + 0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ +}; + +/* LIME UPM B Table Configuration Code */ +static unsigned int UPMTableB[] = +{ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffffc01, /* Words 4 to 7 */ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffffc00, 0xfffffc01, /* Words 20 to 23 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0ffffc01, /* Words 28 to 31 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39 */ + 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43 */ + 0x00fffc04, 0x00fffc04, 0x0ffffc00, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ +}; +#endif |