diff options
Diffstat (limited to 'roms/u-boot/board/solidrun/clearfog')
| -rw-r--r-- | roms/u-boot/board/solidrun/clearfog/Kconfig | 62 | ||||
| -rw-r--r-- | roms/u-boot/board/solidrun/clearfog/MAINTAINERS | 7 | ||||
| -rw-r--r-- | roms/u-boot/board/solidrun/clearfog/Makefile | 5 | ||||
| -rw-r--r-- | roms/u-boot/board/solidrun/clearfog/README | 74 | ||||
| -rw-r--r-- | roms/u-boot/board/solidrun/clearfog/clearfog.c | 262 |
5 files changed, 410 insertions, 0 deletions
diff --git a/roms/u-boot/board/solidrun/clearfog/Kconfig b/roms/u-boot/board/solidrun/clearfog/Kconfig new file mode 100644 index 000000000..cf9525809 --- /dev/null +++ b/roms/u-boot/board/solidrun/clearfog/Kconfig @@ -0,0 +1,62 @@ +menu "ClearFog configuration" + depends on TARGET_CLEARFOG + +config TARGET_CLEARFOG_BASE + bool "Use ClearFog Base static configuration" + help + Use the ClearFog Base as the static configuration instead of the + default which uses the ClearFog Pro. + + Runtime board detection is always attempted and used if available. The + static configuration is used as a fallback in cases where runtime + detection is disabled, is not available in hardware, or otherwise fails. + + Only newer revisions of the ClearFog product line support runtime + detection via additional EEPROM hardware. This option enables selecting + the Base variant for older hardware revisions. + +config CLEARFOG_CON3_SATA + bool "Use CON3 slot in SATA mode" + help + Use the CON3 port with SATA protocol instead of the default PCIe. + The ClearFog port allows usage of either mSATA or miniPCIe + modules, but the desired protocol must be configured at build + time since it affects the SerDes topology layout. + +config CLEARFOG_CON2_SATA + bool "Use CON2 slot in SATA mode" + depends on !TARGET_CLEARFOG_BASE + help + Use the CON2 port with SATA protocol instead of the default PCIe. + The ClearFog port allows usage of either mSATA or miniPCIe + modules, but the desired protocol must be configured at build + time since it affects the SerDes topology layout. + +config CLEARFOG_SFP_25GB + bool "Enable 2.5 Gbps mode for SFP" + help + Set the SFP module connection to support 2.5 Gbps transfer speed for the + SGMII connection (requires a supporting SFP). By default, transfer speed + of 1.25 Gbps is used, suitable for a more common 1 Gbps SFP module. + +config ENV_SIZE + hex "Environment Size" + default 0x10000 + +config ENV_OFFSET + hex "Environment offset" + default 0xF0000 + +config ENV_SECT_SIZE + hex "Environment Sector-Size" + # Use SPI flash erase block size of 4 KiB + default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI || MVEBU_SPL_BOOT_DEVICE_SATA + # Use optimistic 64 KiB erase block, will vary between actual media + default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC || MVEBU_SPL_BOOT_DEVICE_UART + +config SYS_SPI_U_BOOT_OFFS + hex "address of u-boot payload in SPI flash" + default 0x20000 + depends on MVEBU_SPL_BOOT_DEVICE_SPI + +endmenu diff --git a/roms/u-boot/board/solidrun/clearfog/MAINTAINERS b/roms/u-boot/board/solidrun/clearfog/MAINTAINERS new file mode 100644 index 000000000..6646d9620 --- /dev/null +++ b/roms/u-boot/board/solidrun/clearfog/MAINTAINERS @@ -0,0 +1,7 @@ +CLEARFOG BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/soldrun/clearfog/ +F: include/configs/clearfog.h +F: configs/clearfog_defconfig +F: configs/clearfog_gt_8k_defconfig diff --git a/roms/u-boot/board/solidrun/clearfog/Makefile b/roms/u-boot/board/solidrun/clearfog/Makefile new file mode 100644 index 000000000..5cfda3283 --- /dev/null +++ b/roms/u-boot/board/solidrun/clearfog/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> + +obj-y := clearfog.o diff --git a/roms/u-boot/board/solidrun/clearfog/README b/roms/u-boot/board/solidrun/clearfog/README new file mode 100644 index 000000000..9375be849 --- /dev/null +++ b/roms/u-boot/board/solidrun/clearfog/README @@ -0,0 +1,74 @@ +Update from original Marvell U-Boot to mainline U-Boot: +------------------------------------------------------- + +Generate the U-Boot image with these commands: + +$ make clearfog_defconfig +$ make + +The resulting image including the SPL binary with the +full DDR setup is "u-boot-spl.kwb". + +Now all you need to do is copy this image on a SD card. +For example with this command: + +$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 + +Please use the correct device node for your setup instead +of "/dev/sdX" here! + +Install U-Boot on eMMC: +----------------------- + +To make SPL load the main U-Boot image from the eMMC boot partition enable +eMMC boot acknowledgement and boot partition with the following U-Boot +command: + + mmc partconf 0 1 1 0 + +Install U-Boot on eMMC boot partition from Linux running on Clearfog: + + echo 0 > /sys/block/mmcblk0boot0/force_ro + dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0 + +Note that the SD card is not accessible when the Clearfog SOM has eMMC. +Consider initial boot from UART (see below). + +Install U-Boot on SATA: +----------------------- + +When loading the main U-Boot image from raw SATA sector, set +CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR to 0x141. + +Boot selection: +--------------- + +Before powering up the board, boot selection should be done via the SW1 dip +switch (0: OFF, 1: ON): + + - SPI: 00010 + - SD/eMMC: 00111 + - M.2 SSD: 11100 + - UART: 01001 [1] + +[1]: According to SolidRun's manual, 11110 should be used for UART booting on + the ClearFog 'Pro' variant. + However, this doesn't work (anymore) at least on Rev. 2.1 (but '01001' as + mentionend for the 'Base' variant does). + +Boot from UART: +--------------- + +Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5) +to your host. + +Set the SW1 DIP switches to UART boot (see above). + +Run the following command to initiate U-Boot download: + + ./tools/kwboot -b u-boot-spl.kwb /dev/ttyUSBX + +Use the correct UART device node for /dev/ttyUSBX. + +When download finishes start your favorite terminal emulator +on /dev/ttyUSBX. diff --git a/roms/u-boot/board/solidrun/clearfog/clearfog.c b/roms/u-boot/board/solidrun/clearfog/clearfog.c new file mode 100644 index 000000000..c920cf8d6 --- /dev/null +++ b/roms/u-boot/board/solidrun/clearfog/clearfog.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <env.h> +#include <i2c.h> +#include <init.h> +#include <miiphy.h> +#include <net.h> +#include <netdev.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include "../common/tlv_data.h" + +#include "../drivers/ddr/marvell/a38x/ddr3_init.h" +#include <../serdes/a38x/high_speed_env_spec.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-15t1-clearfog" + */ +#define BOARD_GPP_OUT_ENA_LOW 0xffffffff +#define BOARD_GPP_OUT_ENA_MID 0xffffffff + +#define BOARD_GPP_OUT_VAL_LOW 0x0 +#define BOARD_GPP_OUT_VAL_MID 0x0 +#define BOARD_GPP_POL_LOW 0x0 +#define BOARD_GPP_POL_MID 0x0 + +static struct tlv_data cf_tlv_data; + +static void cf_read_tlv_data(void) +{ + static bool read_once; + + if (read_once) + return; + read_once = true; + + read_tlv_data(&cf_tlv_data); +} + +/* The starting board_serdes_map reflects original Clearfog Pro usage */ +static struct serdes_map board_serdes_map[] = { + {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, +}; + +void config_cfbase_serdes_map(void) +{ + board_serdes_map[4].serdes_type = USB3_HOST0; + board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS; + board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE; +} + +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) +{ + cf_read_tlv_data(); + + /* Apply build configuration options before runtime configuration */ + if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB)) + board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS; + + if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) { + board_serdes_map[4].serdes_type = SATA2; + board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS; + board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE; + board_serdes_map[4].swap_rx = 1; + } + + if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) { + board_serdes_map[2].serdes_type = SATA1; + board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS; + board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE; + board_serdes_map[2].swap_rx = 1; + } + + /* Apply runtime detection changes */ + if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) { + board_serdes_map[0].serdes_type = PEX0; + board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS; + board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1; + } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) { + /* handle recognized product as noop, no adjustment required */ + } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) { + config_cfbase_serdes_map(); + } else { + /* + * Fallback to static default. EEPROM TLV support is not + * enabled, runtime detection failed, hardware support is not + * present, EEPROM is corrupt, or an unrecognized product name + * is present. + */ + if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM)) + puts("EEPROM TLV detection failed: "); + puts("Using static config for "); + if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) { + puts("Clearfog Base.\n"); + config_cfbase_serdes_map(); + } else { + puts("Clearfog Pro.\n"); + } + } + + *serdes_map_array = board_serdes_map; + *count = ARRAY_SIZE(board_serdes_map); + return 0; +} + +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct mv_ddr_topology_map board_topology_map = { + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ + MV_DDR_DIE_CAP_4GBIT, /* mem_size */ + MV_DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_wl cas_l */ + MV_DDR_TEMP_LOW, /* temperature */ + MV_DDR_TIM_DEFAULT} }, /* timing */ + BUS_MASK_32BIT, /* Busses mask */ + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ + { {0} }, /* raw spd data */ + {0}, /* timing parameters */ + { {0} }, /* electrical configuration */ + {0,}, /* electrical parameters */ + 0x3, /* clock enable mask */ +}; + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + struct if_params *ifp = &board_topology_map.interface_params[0]; + + cf_read_tlv_data(); + + switch (cf_tlv_data.ram_size) { + case 4: + default: + ifp->memory_size = MV_DDR_DIE_CAP_4GBIT; + break; + case 8: + ifp->memory_size = MV_DDR_DIE_CAP_8GBIT; + break; + } + + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x11111111, MVEBU_MPP_BASE + 0x00); + writel(0x11111111, MVEBU_MPP_BASE + 0x04); + writel(0x10400011, MVEBU_MPP_BASE + 0x08); + writel(0x22043333, MVEBU_MPP_BASE + 0x0c); + writel(0x44400002, MVEBU_MPP_BASE + 0x10); + writel(0x41144004, MVEBU_MPP_BASE + 0x14); + writel(0x40333333, MVEBU_MPP_BASE + 0x18); + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); + + /* Set GPP Out value */ + writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Toggle GPIO41 to reset onboard switch and phy */ + clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); + /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */ + clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); + clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); + mdelay(1); + setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); + mdelay(10); + + return 0; +} + +int checkboard(void) +{ + char *board = "Clearfog Pro"; + if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) + board = "Clearfog Base"; + + cf_read_tlv_data(); + if (strlen(cf_tlv_data.tlv_product_name[0]) > 0) + board = cf_tlv_data.tlv_product_name[0]; + + printf("Board: SolidRun %s", board); + if (strlen(cf_tlv_data.tlv_product_name[1]) > 0) + printf(", %s", cf_tlv_data.tlv_product_name[1]); + puts("\n"); + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} + +int board_late_init(void) +{ + if (env_get("fdtfile")) + return 0; + + cf_read_tlv_data(); + + if (sr_product_is(&cf_tlv_data, "Clearfog Base")) + env_set("fdtfile", "armada-388-clearfog-base.dtb"); + else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4")) + env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb"); + else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8")) + env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb"); + else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) + env_set("fdtfile", "armada-388-clearfog-base.dtb"); + else + env_set("fdtfile", "armada-388-clearfog-pro.dtb"); + + return 0; +} |