diff options
Diffstat (limited to 'roms/u-boot/board/synopsys/iot_devkit')
| -rw-r--r-- | roms/u-boot/board/synopsys/iot_devkit/Kconfig | 12 | ||||
| -rw-r--r-- | roms/u-boot/board/synopsys/iot_devkit/MAINTAINERS | 5 | ||||
| -rw-r--r-- | roms/u-boot/board/synopsys/iot_devkit/Makefile | 7 | ||||
| -rw-r--r-- | roms/u-boot/board/synopsys/iot_devkit/README | 145 | ||||
| -rw-r--r-- | roms/u-boot/board/synopsys/iot_devkit/config.mk | 3 | ||||
| -rw-r--r-- | roms/u-boot/board/synopsys/iot_devkit/iot_devkit.c | 163 | ||||
| -rw-r--r-- | roms/u-boot/board/synopsys/iot_devkit/u-boot.lds | 77 |
7 files changed, 412 insertions, 0 deletions
diff --git a/roms/u-boot/board/synopsys/iot_devkit/Kconfig b/roms/u-boot/board/synopsys/iot_devkit/Kconfig new file mode 100644 index 000000000..ad956b20f --- /dev/null +++ b/roms/u-boot/board/synopsys/iot_devkit/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IOT_DEVKIT + +config SYS_BOARD + default "iot_devkit" + +config SYS_VENDOR + default "synopsys" + +config SYS_CONFIG_NAME + default "iot_devkit" + +endif diff --git a/roms/u-boot/board/synopsys/iot_devkit/MAINTAINERS b/roms/u-boot/board/synopsys/iot_devkit/MAINTAINERS new file mode 100644 index 000000000..06457cfa6 --- /dev/null +++ b/roms/u-boot/board/synopsys/iot_devkit/MAINTAINERS @@ -0,0 +1,5 @@ +IOT DEVKIT BOARD +M: Alexey Brodkin <abrodkin@synopsys.com> +S: Maintained +F: board/synopsys/iot_devkit/ +F: configs/iot_devkit_defconfig diff --git a/roms/u-boot/board/synopsys/iot_devkit/Makefile b/roms/u-boot/board/synopsys/iot_devkit/Makefile new file mode 100644 index 000000000..161602464 --- /dev/null +++ b/roms/u-boot/board/synopsys/iot_devkit/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2018 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += iot_devkit.o diff --git a/roms/u-boot/board/synopsys/iot_devkit/README b/roms/u-boot/board/synopsys/iot_devkit/README new file mode 100644 index 000000000..20c140d93 --- /dev/null +++ b/roms/u-boot/board/synopsys/iot_devkit/README @@ -0,0 +1,145 @@ +================================================================================ +Useful notes on bulding and using of U-Boot on +ARC IoT Development Kit (AKA IoTDK) +================================================================================ + + BOARD OVERVIEW + + The DesignWare ARC IoT Development Kit is a versatile platform that includes + the necessary hardware and software to accelerate software development and + debugging of sensor fusion, voice recognition and face detection designs. + + The ARC IoT Development Kit includes a silicon implementation of the + ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's + 55-nm ultra-low power process, and a rich set of peripherals commonly used + in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. + + The board is shipped with pre-installed U-Boot in non-volatile memory + (eFlash) so on power-on user sees U-Boot start header and command line + prompt which might be used for U-Boot environment fine-tuning, manual + loading and execution of user application binaries etc. + + The board has the following features useful for U-Boot: + * On-board 2-channel FTDI TTL-to-USB converter + - The first channel is used for serial debug port (which makes it possible + to use a serial connection on pretty much any host machine be it + Windows, Linux or Mac). + On Linux machine typucally FTDI serial port would be /dev/ttyUSB0. + There's no HW flow-control and baud-rate is 115200. + + - The second channel is used for built-in Digilent USB JTAG probe. + That means no extra hardware is required to access ARC core from a + debugger on development host. Both proprietary MetaWare debugger and + open source OpenOCD + GDB client are supported. + + - Also with help of this FTDI chip it is possible to reset entire + board with help of a special `rff-ftdi-reset` utility, see: + https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset + + * Micro SD-card slot + - U-Boot expects to see the very first partition on the card formatted as + FAT file-system and uses it for keeping its environment in `uboot.env` + file. Note uboot.env is not just a text file but it is auto-generated + file created by U-Boot on invocation of `saveenv` command. + It contains a checksum which makes this saved environment invalid in + case of maual modification. + + - There might be more useful files on that first FAT partition like + user applications, data files etc. + + * USB OTG connector + - U-Boot may access USB mass-storage devices attached to this connector. + Note only FAT file-system is supported. It might be used for storing + user application binaries as well as micro SD-card mentioned above. + + * The following memories are avaialble on the board: + - eFlash: 256 KiB @ 0x0000_0000 + A non-volatile memory from which ARC core may execute code directly. + Still is is not direcly writable, thus this is not an ordinary RAM. + + - ICCM: 256 KiB @ 0x2000_0000 + Instruction Closely Coupled Memory - fast on-chip memory primary used + for code being executed, still data could be placed in this memory too. + In that sense it's just a general purpose RAM. + + - SRAM: 128 KiB @ 0x3000_0000 + On-chip SRAM. From user perspective is the same as ICCM above. + + - DCCM: 128 KiB @ 0x8000_0000 + Data Closely Coupled Memory is similar to ICCM with a major difference - + ARC core cannot execute code from DCCM. So this is very special RAM + only suitable for data. + + BUILDING U-BOOT + + 1. Configure U-Boot: + ------------------------->8---------------------- + make iot_devkit_defconfig + ------------------------->8---------------------- + + 2. To build Elf file (for example to be used with host debugger via JTAG + connection to the target board): + ------------------------->8---------------------- + make mdbtrick + ------------------------->8---------------------- + + This will produce `u-boot` Elf file. + + 3. To build binary image to be put in "ROM": + ------------------------->8---------------------- + make u-boot.bin + ------------------------->8---------------------- + + + EXECUTING U-BOOT + + 1. The IoTDK board is supposed to auto-start U-Boot image stored in eFlash on + power-on. Note it's possible to update that image - follow instructions in + user's manual. + + 2. Though it is possible to load and start U-Boot as a simple Elf file + via JTAG right in ICCM. For that it's required to re-configure U-Boot + so it gets linked to ICCM address 0x2000_0000 (remember eFlash is not + direcly writable). + Run U-Boot's configuration utility with "make menuconfig", go to + "Boot images" and change "Text Base" from default 0x00000000 to + 0x20000000. Exit & save new configuration. Now run "make mdbtrick" to + build new Elf. + + 2.1. In case of proprietary MetaWare debugger run: + ------------------------->8---------------------- + mdb -digilent u-boot + ------------------------->8---------------------- + + USING U-BOOT + + Note due to limited memory size it's supposed that user will run binary + images of their applications instead of loading Elf files. + + 1. To load and start application binary from micro SD-card execute + the following commands in U-Boot's shell: + ------------------------->8---------------------- + fatload mmc 0 0x20000000 yourapp.bin + go 0x20000000 + ------------------------->8---------------------- + + 2. To load and start application binary from USB mass-storage device execute + the following commands in U-Boot's shell: + ------------------------->8---------------------- + usb start + fatload usb 0x20000000 yourapp.bin + go 0x20000000 + ------------------------->8---------------------- + + 3. To have a sequence of commands executed on U-Boot start put those + commands in "bootcmd" with semicolon between them. + For example to get (1) done automatically: + ------------------------->8---------------------- + setenv bootcmd fatload mmc 0 0x20000000 yourapp.bin\; go 0x20000000 + saveenv + ------------------------->8---------------------- + + 4. To reboot the board just run: + ------------------------->8---------------------- + reset + ------------------------->8---------------------- diff --git a/roms/u-boot/board/synopsys/iot_devkit/config.mk b/roms/u-boot/board/synopsys/iot_devkit/config.mk new file mode 100644 index 000000000..bd8f09ec7 --- /dev/null +++ b/roms/u-boot/board/synopsys/iot_devkit/config.mk @@ -0,0 +1,3 @@ +PLATFORM_CPPFLAGS += -mcpu=arcem -mlittle-endian -mcode-density -mdiv-rem \ + -mswap -mnorm -mmpy-option=6 -mbarrel-shifter +LDSCRIPT = $(srctree)/board/synopsys/iot_devkit/u-boot.lds diff --git a/roms/u-boot/board/synopsys/iot_devkit/iot_devkit.c b/roms/u-boot/board/synopsys/iot_devkit/iot_devkit.c new file mode 100644 index 000000000..650958f94 --- /dev/null +++ b/roms/u-boot/board/synopsys/iot_devkit/iot_devkit.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Synopsys, Inc. All rights reserved. + */ + +#include <common.h> +#include <cpu_func.h> +#include <init.h> +#include <malloc.h> +#include <dwmmc.h> +#include <asm/global_data.h> +#include <linux/bitops.h> +#include <linux/libfdt.h> +#include <fdtdec.h> + +#include <asm/arcregs.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SYSCON_BASE 0xf000a000 +#define AHBCKDIV (void *)(SYSCON_BASE + 0x04) +#define APBCKDIV (void *)(SYSCON_BASE + 0x08) +#define APBCKEN (void *)(SYSCON_BASE + 0x0C) +#define RESET_REG (void *)(SYSCON_BASE + 0x18) +#define CLKSEL (void *)(SYSCON_BASE + 0x24) +#define CLKSTAT (void *)(SYSCON_BASE + 0x28) +#define PLLCON (void *)(SYSCON_BASE + 0x2C) +#define APBCKSEL (void *)(SYSCON_BASE + 0x30) +#define AHBCKEN (void *)(SYSCON_BASE + 0x34) +#define USBPHY_PLL (void *)(SYSCON_BASE + 0x78) +#define USBCFG (void *)(SYSCON_BASE + 0x7c) + +#define PLL_MASK_0 0xffcfffff +#define PLL_MASK_1 0xffcfff00 +#define PLL_MASK_2 0xfbcfff00 + +#define CLKSEL_DEFAULT 0x5a690000 + +static int set_cpu_freq(unsigned int clk) +{ + clk /= 1000000; + + /* Set clk to ext Xtal (LSN value 0) */ + writel(CLKSEL_DEFAULT, CLKSEL); + + switch (clk) { + case 16: + /* Bypass mode */ + return 0; + + case 50: + writel(readl(PLLCON) & PLL_MASK_0, PLLCON); + /* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */ + writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON); + /* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */ + writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON); + break; + + case 72: + writel(readl(PLLCON) & PLL_MASK_0, PLLCON); + /* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */ + writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON); + /* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */ + writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON); + break; + + case 100: + writel(readl(PLLCON) & PLL_MASK_0, PLLCON); + /* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */ + writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON); + /* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */ + writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON); + break; + + case 136: + writel(readl(PLLCON) & PLL_MASK_0, PLLCON); + /* pll_off=1, M=17, N=1, OD=1, PLL_OUT_CLK=136M */ + writel((readl(PLLCON) & PLL_MASK_1) | 0x100111, PLLCON); + /* pll_off=0, M=17, N=1, OD=1, PLL_OUT_CLK=136M */ + writel((readl(PLLCON) & PLL_MASK_2) | 0x100111, PLLCON); + break; + + case 144: + writel(readl(PLLCON) & PLL_MASK_0, PLLCON); + /* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */ + writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON); + /* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */ + writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON); + break; + + default: + return -EINVAL; + } + + while (!(readl(CLKSTAT) & 0x4)) + ; + + /* Set clk from PLL on bus (LSN = 1) */ + writel(CLKSEL_DEFAULT | BIT(0), CLKSEL); + + return 0; +} + +extern u8 __rom_end[]; +extern u8 __ram_start[]; +extern u8 __ram_end[]; + +/* + * Use mach_cpu_init() for .data section copy as board_early_init_f() will be + * too late: initf_dm() will use a value of "av_" variable from not yet + * initialized (by copy) area. + */ +int mach_cpu_init(void) +{ + int offset; + + /* Don't relocate U-Boot */ + gd->flags |= GD_FLG_SKIP_RELOC; + + /* Copy data from ROM to RAM */ + u8 *src = __rom_end; + u8 *dst = __ram_start; + + while (dst < __ram_end) + *dst++ = *src++; + + /* Enable debug uart */ +#define DEBUG_UART_BASE 0x80014000 +#define DEBUG_UART_DLF_OFFSET 0xc0 + write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1); + + offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk"); + if (offset < 0) + return offset; + + gd->cpu_clk = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0); + if (!gd->cpu_clk) + return -EINVAL; + + /* If CPU freq > 100 MHz, divide eFLASH clock by 2 */ + if (gd->cpu_clk > 100000000) { + u32 reg = readl(AHBCKDIV); + + reg &= ~(0xF << 8); + reg |= 2 << 8; + writel(reg, AHBCKDIV); + } + + return set_cpu_freq(gd->cpu_clk); +} + +#define IOTDK_RESET_SEQ 0x55AA6699 + +void reset_cpu(void) +{ + writel(IOTDK_RESET_SEQ, RESET_REG); +} + +int checkboard(void) +{ + puts("Board: Synopsys IoT Development Kit\n"); + return 0; +}; diff --git a/roms/u-boot/board/synopsys/iot_devkit/u-boot.lds b/roms/u-boot/board/synopsys/iot_devkit/u-boot.lds new file mode 100644 index 000000000..d08316870 --- /dev/null +++ b/roms/u-boot/board/synopsys/iot_devkit/u-boot.lds @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +MEMORY { + ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE + RAM : ORIGIN = RAM_DATA_BASE, LENGTH = RAM_DATA_SIZE +} + +OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc") +OUTPUT_ARCH(arc) +ENTRY(_start) +SECTIONS +{ + . = CONFIG_SYS_MONITOR_BASE; + __image_copy_start = .; + .ivt : + { + __ivt_start = .; + KEEP(*(.ivt)); + __ivt_end = .; + } > ROM + + . = ALIGN(1024); + .text : { + __text_start = .; + arch/arc/lib/start.o (.text*) + *(.text*) + __text_end = .; + } > ROM + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } > ROM + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + + /* Mark RAM's LMA */ + . = ALIGN(4); + __rom_end = .; + } > ROM + + .data : { + /* Mark RAM's VMA */ + . = ALIGN(4); + + /* + * Everything between __ram_start and __ram_start will be + * copied from ROM to RAM in board_early_init_f(). + */ + __ram_start = .; + + *(.data*) + + __ram_end = .; + } > RAM AT > ROM + + .bss : { + . = ALIGN(1024); + __bss_start = .; + *(.bss*) + __bss_end = .; + } > RAM + + /* Keep relocation-related symbols to make linker happy */ + __rel_dyn_start = .; + __rel_dyn_end = .; + __image_copy_end = .; + __init_end = .; +} |