aboutsummaryrefslogtreecommitdiffstats
path: root/roms/u-boot/board/sysam
diff options
context:
space:
mode:
Diffstat (limited to 'roms/u-boot/board/sysam')
-rw-r--r--roms/u-boot/board/sysam/amcore/Kconfig22
-rw-r--r--roms/u-boot/board/sysam/amcore/MAINTAINERS6
-rw-r--r--roms/u-boot/board/sysam/amcore/Makefile7
-rw-r--r--roms/u-boot/board/sysam/amcore/amcore.c120
-rw-r--r--roms/u-boot/board/sysam/stmark2/Kconfig15
-rw-r--r--roms/u-boot/board/sysam/stmark2/MAINTAINERS6
-rw-r--r--roms/u-boot/board/sysam/stmark2/Makefile8
-rw-r--r--roms/u-boot/board/sysam/stmark2/sbf_dram_init.S118
-rw-r--r--roms/u-boot/board/sysam/stmark2/stmark2.c48
9 files changed, 350 insertions, 0 deletions
diff --git a/roms/u-boot/board/sysam/amcore/Kconfig b/roms/u-boot/board/sysam/amcore/Kconfig
new file mode 100644
index 000000000..dd9816ec2
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_AMCORE
+
+config SYS_CPU
+ string
+ default "mcf530x"
+
+config SYS_BOARD
+ string
+ default "amcore"
+
+config SYS_VENDOR
+ string
+ default "sysam"
+
+config SYS_CONFIG_NAME
+ string
+ default "amcore"
+
+endif
+
+
+
diff --git a/roms/u-boot/board/sysam/amcore/MAINTAINERS b/roms/u-boot/board/sysam/amcore/MAINTAINERS
new file mode 100644
index 000000000..fe5dd9bf3
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/MAINTAINERS
@@ -0,0 +1,6 @@
+AMCORE BOARD
+M: Angelo Dureghello <angelo@sysam.it>
+S: Maintained
+F: board/sysam/amcore/
+F: include/configs/amcore.h
+F: configs/amcore_defconfig
diff --git a/roms/u-boot/board/sysam/amcore/Makefile b/roms/u-boot/board/sysam/amcore/Makefile
new file mode 100644
index 000000000..051186f0d
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = amcore.o
diff --git a/roms/u-boot/board/sysam/amcore/amcore.c b/roms/u-boot/board/sysam/amcore/amcore.c
new file mode 100644
index 000000000..beab4e9d1
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/amcore.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for Sysam AMCORE (MCF5307 based) board
+ *
+ * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
+ *
+ * This file copies memory testdram() from sandburst/common/sb_common.c
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void init_lcd(void)
+{
+ /* setup for possible K0108 lcd connected on the parallel port */
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_be16(&sim->par, 0x300);
+
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+
+ out_be16(&gpio->paddr, 0xfcff);
+ out_be16(&gpio->padat, 0x0c00);
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("AMCORE v.001(alpha)\n");
+
+ init_lcd();
+
+ return 0;
+}
+
+/*
+ * in dram_init we are here executing from flash
+ * case 1:
+ * is with no ACR/flash cache enabled
+ * nop = 40ns (scope measured)
+ */
+void fudelay(int usec)
+{
+ while (usec--)
+ asm volatile ("nop");
+}
+
+int dram_init(void)
+{
+ u32 dramsize, RC;
+
+ sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
+
+ /*
+ * SDRAM MT48LC4M32B2 details
+ * Memory block 0: 16 MB of SDRAM at address $00000000
+ * Port size: 32-bit port
+ *
+ * Memory block 0 wired as follows:
+ * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
+ * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
+ *
+ * Ensure that there is a delay of at least 100 microseconds from
+ * processor reset to the following code so that the SDRAM is ready
+ * for commands.
+ */
+ fudelay(100);
+
+ /*
+ * DCR
+ * set proper RC as per specification
+ */
+ RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* 0x8000 is the faster option */
+ out_be16(&dc->dcr, 0x8200 | RC);
+
+ /*
+ * DACR0, page mode continuous, CMD on A20 0x0300
+ */
+ out_be32(&dc->dacr0, 0x00003304);
+
+ dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+ out_be32(&dc->dmr0, dramsize|1);
+
+ /* issue a PRECHARGE ALL */
+ out_be32(&dc->dacr0, 0x0000330c);
+ out_be32((u32 *)0x00000004, 0xbeaddeed);
+ /* issue AUTOREFRESH */
+ out_be32(&dc->dacr0, 0x0000b304);
+ /* let refresh occur */
+ fudelay(1);
+
+ out_be32(&dc->dacr0, 0x0000b344);
+ out_be32((u32 *)0x00000c00, 0xbeaddeed);
+
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static struct coldfire_serial_plat mcf5307_serial_plat = {
+ .base = CONFIG_SYS_UART_BASE,
+ .port = 0,
+ .baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DRVINFO(coldfire_serial) = {
+ .name = "serial_coldfire",
+ .plat = &mcf5307_serial_plat,
+};
diff --git a/roms/u-boot/board/sysam/stmark2/Kconfig b/roms/u-boot/board/sysam/stmark2/Kconfig
new file mode 100644
index 000000000..87ab7ab7b
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_STMARK2
+
+config SYS_CPU
+ default "mcf5445x"
+
+config SYS_BOARD
+ default "stmark2"
+
+config SYS_VENDOR
+ default "sysam"
+
+config SYS_CONFIG_NAME
+ default "stmark2"
+
+endif
diff --git a/roms/u-boot/board/sysam/stmark2/MAINTAINERS b/roms/u-boot/board/sysam/stmark2/MAINTAINERS
new file mode 100644
index 000000000..b87f432bb
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/MAINTAINERS
@@ -0,0 +1,6 @@
+STMARK2 BOARD
+M: Angelo Dureghello <angelo@sysam.it>
+S: Maintained
+F: board/sysam/stmark2/
+F: include/configs/stmark2.h
+F: configs/stmark2_defconfig
diff --git a/roms/u-boot/board/sysam/stmark2/Makefile b/roms/u-boot/board/sysam/stmark2/Makefile
new file mode 100644
index 000000000..064a57ea0
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = stmark2.o
+extra-y += sbf_dram_init.o
diff --git a/roms/u-boot/board/sysam/stmark2/sbf_dram_init.S b/roms/u-boot/board/sysam/stmark2/sbf_dram_init.S
new file mode 100644
index 000000000..984b31b9d
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/sbf_dram_init.S
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board-specific early ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ */
+
+.equ PPMCR0, 0xfc04002d
+.equ MSCR_SDRAMC, 0xec094060
+.equ MISCCR2, 0xec09001a
+.equ DDR_RCR, 0xfc0b8180
+.equ DDR_PADCR, 0xfc0b81ac
+.equ DDR_CR00, 0xfc0b8000
+.equ DDR_CR06, 0xfc0b8018
+.equ DDR_CR09, 0xfc0b8024
+.equ DDR_CR40, 0xfc0b80a0
+.equ DDR_CR45, 0xfc0b80b4
+.equ DDR_CR56, 0xfc0b80e0
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+ /* CD46 = DDR on */
+ move.l #PPMCR0, %a1
+ move.b #46, (%a1)
+
+ /* stmark 2, max drive strength */
+ move.l #MSCR_SDRAMC, %a1
+ move.b #1, (%a1)
+
+ /*
+ * use cpu clock, seems more realiable
+ *
+ * DDR2 clock is serviced from DDR controller as input clock / 2
+ * so, if clock comes from
+ * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
+ * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
+ *
+ * .
+ * / \ DDR2 can't be clocked lower than 125Mhz
+ * / ! \ DDR2 init must pass further i/dcache enable test
+ * /_____\
+ * WARNING
+ */
+
+ /* cpu / 2 = 125 Mhz for 480 Mhz pll */
+ move.l #MISCCR2, %a1
+ move.w #0xa01d, (%a1)
+
+ /* DDR force sw reset settings */
+ move.l #DDR_RCR, %a1
+ move.l #0x00000000, (%a1)
+ move.l #0x40000000, (%a1)
+
+ /*
+ * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
+ * 500/700 mV are ok
+ */
+ move.l #DDR_PADCR, %a1
+ move.l #0x01030203, (%a1) /* as freescale tower */
+
+ move.l #DDR_CR00, %a1
+ move.l #0x01010101, (%a1)+ /* 0x00 */
+ move.l #0x00000101, (%a1)+ /* 0x04 */
+ move.l #0x01010100, (%a1)+ /* 0x08 */
+ move.l #0x01010000, (%a1)+ /* 0x0C */
+ move.l #0x00010101, (%a1)+ /* 0x10 */
+ move.l #DDR_CR06, %a1
+ move.l #0x00010100, (%a1)+ /* 0x18 */
+ move.l #0x00000001, (%a1)+ /* 0x1C */
+ move.l #0x01000001, (%a1)+ /* 0x20 */
+ move.l #0x00000100, (%a1)+ /* 0x24 */
+ move.l #0x00010001, (%a1)+ /* 0x28 */
+ move.l #0x00000200, (%a1)+ /* 0x2C */
+ move.l #0x01000002, (%a1)+ /* 0x30 */
+ move.l #0x00000000, (%a1)+ /* 0x34 */
+ move.l #0x00000100, (%a1)+ /* 0x38 */
+ move.l #0x02000100, (%a1)+ /* 0x3C */
+ move.l #0x02000407, (%a1)+ /* 0x40 */
+ move.l #0x02030007, (%a1)+ /* 0x44 */
+ move.l #0x02000100, (%a1)+ /* 0x48 */
+ move.l #0x0A030203, (%a1)+ /* 0x4C */
+ move.l #0x00020708, (%a1)+ /* 0x50 */
+ move.l #0x00050008, (%a1)+ /* 0x54 */
+ move.l #0x04030002, (%a1)+ /* 0x58 */
+ move.l #0x00000004, (%a1)+ /* 0x5C */
+ move.l #0x020A0000, (%a1)+ /* 0x60 */
+ move.l #0x0C00000E, (%a1)+ /* 0x64 */
+ move.l #0x00002004, (%a1)+ /* 0x68 */
+ move.l #0x00000000, (%a1)+ /* 0x6C */
+ move.l #0x00100010, (%a1)+ /* 0x70 */
+ move.l #0x00100010, (%a1)+ /* 0x74 */
+ move.l #0x00000000, (%a1)+ /* 0x78 */
+ move.l #0x07990000, (%a1)+ /* 0x7C */
+ move.l #DDR_CR40, %a1
+ move.l #0x00000000, (%a1)+ /* 0xA0 */
+ move.l #0x00C80064, (%a1)+ /* 0xA4 */
+ move.l #0x44520002, (%a1)+ /* 0xA8 */
+ move.l #0x00C80023, (%a1)+ /* 0xAC */
+ move.l #DDR_CR45, %a1
+ move.l #0x0000C350, (%a1) /* 0xB4 */
+ move.l #DDR_CR56, %a1
+ move.l #0x04000000, (%a1)+ /* 0xE0 */
+ move.l #0x03000304, (%a1)+ /* 0xE4 */
+ move.l #0x40040000, (%a1)+ /* 0xE8 */
+ move.l #0xC0004004, (%a1)+ /* 0xEC */
+ move.l #0x0642C000, (%a1)+ /* 0xF0 */
+ move.l #0x00000642, (%a1)+ /* 0xF4 */
+ move.l #DDR_CR09, %a1
+ tpf
+ move.l #0x01000100, (%a1) /* 0x24 */
+
+ move.l #0x2000, %d1
+ bsr asm_delay
+
+
+ rts
diff --git a/roms/u-boot/board/sysam/stmark2/stmark2.c b/roms/u-boot/board/sysam/stmark2/stmark2.c
new file mode 100644
index 000000000..d48da48b6
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/stmark2.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board-specific init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spi.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ /*
+ * need to to:
+ * Check serial flash size. if 2mb evb, else 8mb demo
+ */
+ puts("Board: ");
+ puts("Sysam stmark2\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ u32 dramsize;
+
+ /*
+ * Serial Boot: The dram is already initialized in start.S
+ * only require to return DRAM size
+ */
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ gd->ram_size = dramsize;
+
+ return 0;
+}
+
+int testdram(void)
+{
+ return 0;
+}