diff options
Diffstat (limited to 'roms/u-boot/board/timll/devkit3250')
| -rw-r--r-- | roms/u-boot/board/timll/devkit3250/Kconfig | 12 | ||||
| -rw-r--r-- | roms/u-boot/board/timll/devkit3250/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/timll/devkit3250/Makefile | 7 | ||||
| -rw-r--r-- | roms/u-boot/board/timll/devkit3250/devkit3250.c | 83 | ||||
| -rw-r--r-- | roms/u-boot/board/timll/devkit3250/devkit3250_spl.c | 67 |
5 files changed, 175 insertions, 0 deletions
diff --git a/roms/u-boot/board/timll/devkit3250/Kconfig b/roms/u-boot/board/timll/devkit3250/Kconfig new file mode 100644 index 000000000..5129c2dca --- /dev/null +++ b/roms/u-boot/board/timll/devkit3250/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DEVKIT3250 + +config SYS_BOARD + default "devkit3250" + +config SYS_VENDOR + default "timll" + +config SYS_CONFIG_NAME + default "devkit3250" + +endif diff --git a/roms/u-boot/board/timll/devkit3250/MAINTAINERS b/roms/u-boot/board/timll/devkit3250/MAINTAINERS new file mode 100644 index 000000000..cb93563fe --- /dev/null +++ b/roms/u-boot/board/timll/devkit3250/MAINTAINERS @@ -0,0 +1,6 @@ +DEVKIT3250 BOARD +M: Vladimir Zapolskiy <vz@mleia.com> +S: Maintained +F: board/timll/devkit3250/ +F: include/configs/devkit3250.h +F: configs/devkit3250_defconfig diff --git a/roms/u-boot/board/timll/devkit3250/Makefile b/roms/u-boot/board/timll/devkit3250/Makefile new file mode 100644 index 000000000..056813995 --- /dev/null +++ b/roms/u-boot/board/timll/devkit3250/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> + +obj-y := devkit3250.o +obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o diff --git a/roms/u-boot/board/timll/devkit3250/devkit3250.c b/roms/u-boot/board/timll/devkit3250/devkit3250.c new file mode 100644 index 000000000..3c744b943 --- /dev/null +++ b/roms/u-boot/board/timll/devkit3250/devkit3250.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Embest/Timll DevKit3250 board support + * + * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clk.h> +#include <asm/arch/cpu.h> +#include <asm/arch/emc.h> +#include <asm/arch/wdt.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <linux/delay.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; + +void reset_periph(void) +{ + /* This function resets peripherals by triggering RESOUT_N */ + setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); + writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); + udelay(300); + + writel(0, &wdt->mctrl); + clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); + + /* Such a long delay is needed to initialize SMSC phy */ + udelay(10000); +} + +int board_early_init_f(void) +{ + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_i2c_init(1); + lpc32xx_i2c_init(2); + lpc32xx_ssp_init(); + lpc32xx_mac_init(); + + /* + * nWP may be controlled by GPO19, but unpopulated by default R23 + * makes no sense to configure this GPIO level, nWP is always high + */ + lpc32xx_slc_nand_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_SYS_FLASH_CFI + /* Use 16-bit memory interface for NOR Flash */ + emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT; + + /* Change the NOR timings to optimum value to get maximum bandwidth */ + emc->stat[0].waitwen = EMC_STAT_WAITWEN(1); + emc->stat[0].waitoen = EMC_STAT_WAITOEN(0); + emc->stat[0].waitrd = EMC_STAT_WAITRD(12); + emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12); + emc->stat[0].waitwr = EMC_STAT_WAITWR(5); + emc->stat[0].waitturn = EMC_STAT_WAITTURN(2); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} diff --git a/roms/u-boot/board/timll/devkit3250/devkit3250_spl.c b/roms/u-boot/board/timll/devkit3250/devkit3250_spl.c new file mode 100644 index 000000000..47af78ae0 --- /dev/null +++ b/roms/u-boot/board/timll/devkit3250/devkit3250_spl.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Timll DevKit3250 board support, SPL board configuration + * + * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> +#include <asm/arch/emc.h> +#include <asm/arch-lpc32xx/gpio.h> +#include <spl.h> + +static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; + +/* + * SDRAM K4S561632N-LC60 settings are selected in assumption that + * SDRAM clock may be set up to 166 MHz, however at the moment + * it is 104 MHz. Most delay values are converted to be a multiple of + * base clock, and precise pinned values are not needed here. + */ +struct emc_dram_settings dram_64mb = { + .cmddelay = 0x0001C000, + .config0 = 0x00005682, + .rascas0 = 0x00000302, + .rdconfig = 0x00000011, /* undocumented but crucial value */ + + .trp = 83333333, + .tras = 23809524, + .tsrex = 12500000, + .twr = 83000000, /* tWR = tRDL = 2 CLK */ + .trc = 15384616, + .trfc = 15384616, + .txsr = 12500000, + .trrd = 1, + .tmrd = 1, + .tcdlr = 0, + + .refresh = 130000, /* 800 clock cycles */ + + .mode = 0x00018000, + .emode = 0x02000000, +}; + +void spl_board_init(void) +{ + /* First of all silence buzzer controlled by GPO_20 */ + writel((1 << 20), &gpio->p3_outp_clr); + + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + preloader_console_init(); + + ddr_init(&dram_64mb); + + /* + * NAND initialization is done by nand_init(), + * here just enable NAND SLC clocks + */ + lpc32xx_slc_nand_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NAND; +} |