diff options
Diffstat (limited to 'bsp/meta-freescale-3rdparty/recipes-bsp')
67 files changed, 8800 insertions, 273 deletions
diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf-lx2160acex7/0001-plat-nxp-Add-lx2160acex7-module-support.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf-lx2160acex7/0001-plat-nxp-Add-lx2160acex7-module-support.patch new file mode 100644 index 00000000..429a679e --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf-lx2160acex7/0001-plat-nxp-Add-lx2160acex7-module-support.patch @@ -0,0 +1,370 @@ +From 64bd53306e0301e707a52be9f4f7121c87cd6f7d Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 13:17:54 +0300 +Subject: [PATCH] plat/nxp: Add lx2160acex7 module support + +Adds SolidRun's LX2160A based SoC COM express type 7 module support. +The patch is based on LX2160ARDB board and modifies the support to two +SO-DIMMs DDR4 support on I2C address 0x50 and 0x52. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c | 77 ++++++++ + plat/nxp/soc-lx2160/lx2160acex7/platform.mk | 16 ++ + .../nxp/soc-lx2160/lx2160acex7/platform_def.h | 187 ++++++++++++++++++ + plat/nxp/soc-lx2160/lx2160acex7/policy.h | 40 ++++ + 4 files changed, 320 insertions(+) + create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c + create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/platform.mk + create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/platform_def.h + create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/policy.h + +diff --git a/plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c b/plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c +new file mode 100644 +index 00000000..d0bcdf46 +--- /dev/null ++++ b/plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c +@@ -0,0 +1,77 @@ ++/* ++ * Copyright 2019 SolidRun ltd. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ * Author Rabeeh Khoury <rabeeh@solid-run.com> ++ */ ++ ++#include <platform_def.h> ++#include <stdint.h> ++#include <stdio.h> ++#include <stdlib.h> ++#include <stdbool.h> ++#include <debug.h> ++#include <errno.h> ++#include <utils.h> ++#include <string.h> ++#include <ddr.h> ++#include <i2c.h> ++ ++int ddr_board_options(struct ddr_info *priv) ++{ ++ struct memctl_opt *popts = &priv->opt; ++ ++ popts->vref_dimm = 0x24; /* range 1, 83.4% */ ++ popts->rtt_override = 0; ++ popts->rtt_park = 240; ++ popts->otf_burst_chop_en = 0; ++ popts->burst_length = DDR_BL8; ++ popts->trwt_override = 1; ++ popts->bstopre = 0; /* auto precharge */ ++ popts->addr_hash = 1; ++ popts->trwt = 0x3; ++ popts->twrt = 0x3; ++ popts->trrt = 0x3; ++ popts->twwt = 0x3; ++ popts->vref_phy = 0x60; /* 75% */ ++ popts->odt = 48; ++ popts->phy_tx_impedance = 48; ++ ++ return 0; ++} ++ ++long long _init_ddr(void) ++{ ++ int spd_addr[] = { 0x51, 0x53 }; ++ struct ddr_info info; ++ struct sysinfo sys; ++ long long dram_size; ++ ++ zeromem(&sys, sizeof(sys)); ++ get_clocks(&sys); ++ debug("platform clock %lu\n", sys.freq_platform); ++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); ++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); ++ ++ zeromem(&info, sizeof(info)); ++ ++ /* Set two DDRC. Unused DDRC will be removed automatically. */ ++ info.num_ctlrs = 2; ++ info.spd_addr = spd_addr; ++ info.ddr[0] = (void *)NXP_DDR_ADDR; ++ info.ddr[1] = (void *)NXP_DDR2_ADDR; ++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; ++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; ++ info.clk = get_ddr_freq(&sys, 0); ++ if (!info.clk) ++ info.clk = get_ddr_freq(&sys, 1); ++ info.dimm_on_ctlr = 1; ++ ++ dram_size = dram_init(&info); ++ ++ if (dram_size < 0) ++ ERROR("DDR init failed.\n"); ++ ++ return dram_size; ++} +diff --git a/plat/nxp/soc-lx2160/lx2160acex7/platform.mk b/plat/nxp/soc-lx2160/lx2160acex7/platform.mk +new file mode 100644 +index 00000000..490f82f8 +--- /dev/null ++++ b/plat/nxp/soc-lx2160/lx2160acex7/platform.mk +@@ -0,0 +1,16 @@ ++# ++# Copyright 2019 SolidRun ltd. ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++# Author Rabeeh Khoury <rabeeh@solid-run.com> ++ ++# board-specific build parameters ++BOOT_MODE := flexspi_nor ++BOARD := acex7 ++ ++ # get SoC common build parameters ++include plat/nxp/soc-lx2160/soc.mk ++ ++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c ++ +diff --git a/plat/nxp/soc-lx2160/lx2160acex7/platform_def.h b/plat/nxp/soc-lx2160/lx2160acex7/platform_def.h +new file mode 100644 +index 00000000..614f0342 +--- /dev/null ++++ b/plat/nxp/soc-lx2160/lx2160acex7/platform_def.h +@@ -0,0 +1,187 @@ ++/* ++ * Copyright 2019 SolidRun ltd. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ * Author: Rabeeh Khoury <rabeeh@solid-run.com> ++ */ ++ ++#ifndef __PLATFORM_DEF_H__ ++#define __PLATFORM_DEF_H__ ++ ++#include <arch.h> ++/* Certain ARM files require defines from this file */ ++#include <tbbr_img_def.h> ++/* From ARM :-> Has some common defines ARM requires */ ++#include <common_def.h> ++/* Soc specific defines */ ++#include <soc.h> ++/* include the platform-level security policy */ ++#include <policy.h> ++ ++#if defined(IMAGE_BL2) ++#define SEC_MEM_NON_COHERENT ++#endif ++/* Special value used to verify platform parameters from BL2 to BL31 */ ++ ++/* TBD -- Check and get back if this value is same for all platforms */ ++#define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL ++ ++/****************************************************************************** ++ * Board specific defines ++ *****************************************************************************/ ++ ++#define NXP_SYSCLK_FREQ 100000000 ++#define NXP_DDRCLK_FREQ 100000000 ++ ++/* UART related definition */ ++#define NXP_CONSOLE_ADDR NXP_UART_ADDR ++#define NXP_CONSOLE_BAUDRATE 115200 ++ ++#define NXP_SPD_EEPROM0 0x51 ++ ++#define DDRC_NUM_DIMM 1 ++#define CONFIG_DDR_ECC_EN ++#define CONFIG_DDR_ADDR_DEC /* enable address decoding feature */ ++ ++#define PLAT_DEF_DRAM0_SIZE 0x80000000 /* 2G */ ++ ++/* Board specific - size of QSPI Flash on board */ ++#if FLEXSPI_NOR_BOOT ++#define NXP_FLEXSPI_FLASH_SIZE 0x10000000 ++#endif ++/* TBD Put all memory specific defines here */ ++ ++/****************************************************************************** ++ * Required platform porting definitions common to all ARM standard platforms ++ *****************************************************************************/ ++ ++/* Size of cacheable stacks */ ++#if defined(IMAGE_BL2) ++#if defined(TRUSTED_BOARD_BOOT) ++#define PLATFORM_STACK_SIZE 0x2000 ++#else ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++#elif defined(IMAGE_BL31) ++#define PLATFORM_STACK_SIZE 0x1000 ++#endif ++ ++#define FIRMWARE_WELCOME_STR_LS_BL2 "Welcome to LX2160 BL2 Phase\n" ++#define FIRMWARE_WELCOME_STR_LS_BL31 "Welcome to LX2160 BL31 Phase\n" ++ ++/* This is common for all platforms where ++ * 64K is reserved for Secure memory ++ */ ++/* 64M Secure Memory */ ++#define NXP_SECURE_DRAM_SIZE (64 * 1024 * 1024) ++ ++/* 2M Secure EL1 Payload Shared Memory */ ++#define NXP_SP_SHRD_DRAM_SIZE (2 * 1024 * 1024) ++ ++/* Non secure memory */ ++#define NXP_NS_DRAM_SIZE (NXP_DRAM0_SIZE - \ ++ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) ++ ++#define NXP_NS_DRAM_ADDR NXP_DRAM0_ADDR ++ ++#ifdef TEST_BL31 ++#define NXP_SECURE_DRAM_ADDR 0 ++#else ++#define NXP_SECURE_DRAM_ADDR (NXP_NS_DRAM_ADDR + NXP_DRAM0_SIZE - \ ++ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) ++#endif ++ ++#define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + NXP_DRAM0_SIZE \ ++ - NXP_SP_SHRD_DRAM_SIZE) ++ ++#define BL2_BASE (NXP_OCRAM_ADDR + NXP_ROM_RSVD + CSF_HDR_SZ) ++#ifdef SD_BOOT ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE) ++#else ++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) ++#endif ++#define BL2_TEXT_LIMIT (BL2_LIMIT) ++ ++/* 2 MB reserved in secure memory for DDR */ ++#define BL31_BASE NXP_SECURE_DRAM_ADDR ++#define BL31_SIZE (0x200000) ++#define BL31_LIMIT (BL31_BASE + BL31_SIZE) ++ ++/* Put BL32 in secure memory */ ++#define BL32_BASE (NXP_SECURE_DRAM_ADDR + BL31_SIZE) ++#define BL32_LIMIT (NXP_SECURE_DRAM_ADDR + \ ++ NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE) ++ ++/* BL33 memory region */ ++/* Hardcoded based on current address in u-boot */ ++#define BL33_BASE 0x82000000 ++#define BL33_LIMIT (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE) ++ ++/* SD block buffer */ ++#define NXP_SD_BLOCK_BUF_SIZE (0xC000) ++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE) ++ ++#define PHY_GEN2_FW_IMAGE_BUFFER (ULL(0x18000000) + CSF_HDR_SZ) ++ ++/* IO defines as needed by IO driver framework */ ++/* TBD Add how to reach these numbers */ ++#define MAX_IO_DEVICES 4 ++#define MAX_IO_BLOCK_DEVICES 1 ++#define MAX_IO_HANDLES 4 ++ ++ ++/* ++ * FIP image defines - Offset at which FIP Image would be present ++ * Image would include Bl31 , Bl33 and Bl32 (optional) ++ */ ++#ifdef POLICY_FUSE_PROVISION ++#define MAX_FIP_DEVICES 3 ++#define FUSE_BUF ULL(0x81000000) ++#define FUSE_SZ 0x80000 ++#endif ++ ++#ifndef MAX_FIP_DEVICES ++#define MAX_FIP_DEVICES 2 ++#endif ++ ++#define PLAT_FIP_OFFSET 0x100000 ++#define PLAT_FIP_MAX_SIZE 0x400000 ++ ++/* Check if this size can be determined from array size */ ++#if defined(IMAGE_BL2) ++#define MAX_MMAP_REGIONS 8 ++#define MAX_XLAT_TABLES 6 ++#elif defined(IMAGE_BL31) ++#define MAX_MMAP_REGIONS 9 ++#define MAX_XLAT_TABLES 9 ++#elif defined(IMAGE_BL32) ++#define MAX_MMAP_REGIONS 8 ++#define MAX_XLAT_TABLES 9 ++#endif ++ ++/******************************************************************************/ ++/* ++ * ID of the secure physical generic timer interrupt used by the BL32. ++ */ ++#define BL32_IRQ_SEC_PHY_TIMER 29 ++ ++#define BL31_WDOG_SEC 89 ++/* ++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 ++ * terminology. On a GICv2 system or mode, the lists will be merged and treated ++ * as Group 0 interrupts. ++ */ ++#define PLAT_LS_G1S_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE) ++ ++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ ++#define PLAT_LS_G0_IRQ_PROPS(grp) \ ++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_EDGE), \ ++ INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ ++ GIC_INTR_CFG_LEVEL) ++ ++ ++#endif +diff --git a/plat/nxp/soc-lx2160/lx2160acex7/policy.h b/plat/nxp/soc-lx2160/lx2160acex7/policy.h +new file mode 100644 +index 00000000..deae979c +--- /dev/null ++++ b/plat/nxp/soc-lx2160/lx2160acex7/policy.h +@@ -0,0 +1,40 @@ ++/* ++ * Copyright 2019 SolidRun ltd. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * ++ * Author : Rabeeh Khoury <rabeeh@solid-run.com> ++ */ ++ ++/*---------------------------------------------------------------------------*/ ++ ++#ifndef _POLICY_H ++#define _POLICY_H ++ ++ // the following defines affect the PLATFORM SECURITY POLICY ++ ++ // set this to 0x0 if the platform is not using/responding to ECC errors ++ // set this to 0x1 if ECC is being used (we have to do some init) ++#define POLICY_USING_ECC 0x0 ++ ++ // Set this to 0x0 to leave the default SMMU page size in sACR ++ // Set this to 0x1 to change the SMMU page size to 64K ++#define POLICY_SMMU_PAGESZ_64K 0x1 ++ ++/* ++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I ++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7 ++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23 ++ */ ++#define POLICY_PERF_WRIOP 0 ++ ++ /* ++ * set this to '1' if the debug clocks need to remain enabled during ++ * system entry to low-power (LPM20) - this should only be necessary ++ * for testing and NEVER set for normal production ++ */ ++#define POLICY_DEBUG_ENABLE 0 ++ ++//----------------------------------------------------------------------------- ++ ++#endif // _POLICY_H +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf-lx2160acex7/0002-plat-nxp-lx2160a-auto-boot.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf-lx2160acex7/0002-plat-nxp-lx2160a-auto-boot.patch new file mode 100644 index 00000000..9a84b72a --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf-lx2160acex7/0002-plat-nxp-lx2160a-auto-boot.patch @@ -0,0 +1,194 @@ +From b5401a18ad8ade8f12a12171169f99214c7126e3 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 24 Mar 2020 02:48:34 +0200 +Subject: [PATCH 2/2] plat/nxp: lx2160a auto boot + +This patch adds support to patch RCW that already has SD/eMMC/SPI boot +support embedded with conditional load and jump. +The idea is to look for SD/eMMC/SPI boot, and modify src/dst/size +address with the correct values; rather than adding blockread at the end +of RCW code. + +With this patch images are unified and can be used to boot from SD / +eMMC and SPI. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + plat/nxp/common/common.mk | 5 +++ + plat/nxp/tools/create_pbl.c | 79 ++++++++++++++++++++++++++++--------- + 2 files changed, 66 insertions(+), 18 deletions(-) + +diff --git a/plat/nxp/common/common.mk b/plat/nxp/common/common.mk +index a80990740..e7e5f3879 100644 +--- a/plat/nxp/common/common.mk ++++ b/plat/nxp/common/common.mk +@@ -148,6 +148,11 @@ BOOT_DEV_SOURCES = ${PLAT_DRIVERS_PATH}/sd/sd_mmc.c \ + else ifeq (${BOOT_MODE}, flexspi_nor) + $(eval $(call add_define,FLEXSPI_NOR_BOOT)) + BOOT_DEV_SOURCES = ${PLAT_DRIVERS_PATH}/flexspi/nor/flexspi_nor.c ++else ifeq (${BOOT_MODE}, auto) ++$(eval $(call add_define,FLEXSPI_NOR_BOOT)) ++BOOT_DEV_SOURCES = ${PLAT_DRIVERS_PATH}/flexspi/nor/flexspi_nor.c \ ++ ${PLAT_DRIVERS_PATH}/sd/sd_mmc.c \ ++ drivers/io/io_block.c + endif + + # DDR driver needs to be enabled by default +diff --git a/plat/nxp/tools/create_pbl.c b/plat/nxp/tools/create_pbl.c +index 5a08472be..7ee085757 100644 +--- a/plat/nxp/tools/create_pbl.c ++++ b/plat/nxp/tools/create_pbl.c +@@ -67,6 +67,7 @@ typedef enum { + FLXSPI_NOR_BOOT, + FLXSPI_NAND_BOOT, + FLXSPI_NAND4K_BOOT, ++ AUTO_BOOT, + MAX_BOOT /* must be last item in list */ + } boot_src_t; + +@@ -194,7 +195,7 @@ struct pbl_image { + #define SOC_LS2088 2088 + #define SOC_LX2160 2160 + +-static uint32_t pbl_size; ++static uint32_t pbl_size = 0; + bool sb_flag = false; + + /*************************************************************************** +@@ -503,7 +504,6 @@ int add_boot_ptr_cmd(FILE *fp_rcw_pbi_op) + goto bootptr_err; + } + } +- + printf("\nBoot Location Pointer= %x\n", BYTE_SWAP_32(pblimg.ep)); + ret = SUCCESS; + +@@ -697,6 +697,8 @@ int main(int argc, char **argv) + int ret = FAILURE; + bool bootptr_flag = false; + enum stop_command flag_stop_cmd = CRC_STOP_COMMAND;; ++ int skip = 0; ++ uint32_t saved_src; + + /* Initializing the global structure to zero. */ + memset(&pblimg, 0x0, sizeof(struct pbl_image)); +@@ -797,6 +799,8 @@ int main(int argc, char **argv) + pblimg.boot_src = FLXSPI_NAND_BOOT; + else if (!strcmp(optarg, "flexspi_nand2k")) + pblimg.boot_src = FLXSPI_NAND4K_BOOT; ++ else if (!strcmp(optarg, "auto")) ++ pblimg.boot_src = AUTO_BOOT; + else { + printf("CMD Error: Invalid boot source.\n"); + goto exit_main; +@@ -902,13 +906,14 @@ int main(int argc, char **argv) + printf("%s: Error reading PBI Cmd.\n", __func__); + goto exit_main; + } +- while (word != 0x808f0000 && word != 0x80ff0000) { ++ saved_src = pblimg.src_addr; ++ while (word != 0x808f0000 && word != 0x80ff0000) { + pbl_size++; + /* 11th words in RCW has PBL length. Update it + * with new length. 2 comamnds get added + * Block copy + CCSR Write/CSF header write + */ +- if (pbl_size == 11) { ++ if ((pbl_size == 11) && (pblimg.boot_src != AUTO_BOOT)) { + word_1 = (word & PBI_LEN_MASK) + + (PBI_LEN_ADD << 20); + word = word & ~PBI_LEN_MASK; +@@ -923,8 +928,44 @@ int main(int argc, char **argv) + goto exit_main; + } + } +- if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK, +- fp_rcw_pbi_op) != NUM_MEM_BLOCK) { ++ if (pblimg.boot_src == AUTO_BOOT) { ++ if (word == 0x80000008) { ++ printf ("Found SD boot at %d\n",pbl_size); ++ pblimg.boot_src = SD_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip = 6; ++ } else skip=4; ++ } ++ if (word == 0x80000009) { ++ printf ("Found eMMC boot at %d\n",pbl_size); ++ pblimg.boot_src = EMMC_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip = 6; ++ } else skip=4; ++ } ++ if (word == 0x8000000f) { ++ printf ("Found SPI boot at %d\n",pbl_size); ++ pblimg.boot_src = FLXSPI_NOR_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip = 6; ++ } else skip=4; ++ } ++ } ++ if (!skip && ++ (fwrite(&word, sizeof(word), NUM_MEM_BLOCK, ++ fp_rcw_pbi_op) != NUM_MEM_BLOCK)) { + printf("%s: [CH3] Error in Writing PBI Words\n", + __func__); + goto exit_main; +@@ -941,8 +982,9 @@ int main(int argc, char **argv) + } else if (word == STOP_CMD_ARM_CH3){ + flag_stop_cmd = STOP_COMMAND; + } ++ if (skip) skip--; + } +- if (bootptr_flag == true) { ++ if ((pblimg.boot_src != AUTO_BOOT) && (bootptr_flag == true)) { + /* Add command to set boot_loc ptr */ + ret = add_boot_ptr_cmd(fp_rcw_pbi_op); + if (ret != SUCCESS) { +@@ -953,18 +995,19 @@ int main(int argc, char **argv) + } + + /* Write acs write commands to output file */ +- ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args); +- if (ret != SUCCESS) { +- printf("%s: Function add_blk_cpy_cmd return failure.\n", +- __func__); +- goto exit_main; +- } +- ++ if (pblimg.boot_src != AUTO_BOOT) { ++ ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ if (ret != SUCCESS) { ++ printf("%s: Function add_blk_cpy_cmd return failure.\n", ++ __func__); ++ goto exit_main; ++ } ++ } + /* Add stop command after adding pbi commands */ +- ret = add_pbi_stop_cmd(fp_rcw_pbi_op, flag_stop_cmd); +- if (ret != SUCCESS) { +- goto exit_main; +- } ++ ret = add_pbi_stop_cmd(fp_rcw_pbi_op, flag_stop_cmd); ++ if (ret != SUCCESS) { ++ goto exit_main; ++ } + + break; + +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf_git.bbappend b/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf_git.bbappend new file mode 100644 index 00000000..9f3171da --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/atf/atf_git.bbappend @@ -0,0 +1,6 @@ +FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:" + +SRC_URI_append_lx2160acex7 = "\ + file://0001-plat-nxp-Add-lx2160acex7-module-support.patch \ + file://0002-plat-nxp-lx2160a-auto-boot.patch \ +" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/bcm4339-nvram-config.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/bcm4339-nvram-config.bb index bfd5ecf0..d87a2fd1 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/bcm4339-nvram-config.bb +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/bcm4339-nvram-config.bb @@ -5,4 +5,4 @@ include broadcom-nvram-config.inc CHIP_MODEL = "4339" -COMPATIBLE_MACHINE = "(imx7d-pico)" +COMPATIBLE_MACHINE = "(imx7d-pico|imx6ul-pico|imx6qdl-pico)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/files/imx6qdl-pico/brcmfmac4339-sdio.txt b/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/files/imx6qdl-pico/brcmfmac4339-sdio.txt new file mode 100644 index 00000000..1ddd9295 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/files/imx6qdl-pico/brcmfmac4339-sdio.txt @@ -0,0 +1,99 @@ +#AP6335_NVRAM_V1.5_03112014 +NVRAMRev=$Rev: 410316 $ +sromrev=11 +boardrev=0x1203 +boardtype=0x06c5 +boardflags=0x00000c01 +boardflags2=0x00002000 +boardflags3=0x101188 +macaddr=00:90:4c:c5:12:38 +ccode=0 +regrev=0 +antswitch=0 +pdgain2g=7 +pdgain5g=7 +tworangetssi2g=0 +tworangetssi5g=0 +femctrl=7 +pcieingress_war=15 +vendid=0x14e4 +devid=0x43ae +manfid=0x2d0 +nocrc=1 +otpimagesize=502 +xtalfreq=37400 +extpagain2g=2 +pdetrange2g=2 +extpagain5g=2 +pdetrange5g=2 +rxgains2gelnagaina0=0 +rxgains2gtrisoa0=7 +rxgains2gtrelnabypa0=0 +rxgains5gelnagaina0=0 +rxgains5gtrisoa0=11 +rxgains5gtrelnabypa0=0 +rxchain=1 +txchain=1 +aa2g=1 +aa5g=1 +tssipos5g=0 +tssipos2g=0 +pa2ga0=-161,6269,-723 +pa2gccka0=-116,7568,-852 +pa5ga0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pa5gbw40a0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pa5gbw80a0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pdoffset40ma0=0 +pdoffset80ma0=0 +pdoffsetcckma0=0 +maxp2ga0=75 +maxp5ga0=64,64,72,72 +cckbw202gpo=0x0000 +cckbw20ul2gpo=0x0 +mcsbw202gpo=0x99445533 +mcsbw402gpo=0x99775533 +dot11agofdmhrbw202gpo=0x2233 +ofdmlrbw202gpo=0x0000 +tssifloor2g=500 +mcsbw205glpo=0x66333330 +mcsbw405glpo=0x66665530 +mcsbw805glpo=0xAA555530 +mcsbw1605glpo=0x99555530 +mcsbw205gmpo=0x99BB5530 +mcsbw405gmpo=0x99BB5530 +mcsbw805gmpo=0xEE555530 +mcsbw1605gmpo=0x99555530 +mcsbw205ghpo=0x99995530 +mcsbw405ghpo=0x99BB5530 +mcsbw805ghpo=0xEE555530 +mcsbw1605ghpo=0x99555530 +mcslr5glpo=0x0000 +mcslr5gmpo=0x0000 +mcslr5ghpo=0x0000 +sb20in40hrrpo=0x0 +sb20in80and160hr5glpo=0x0 +sb40and80hr5glpo=0x0 +sb20in80and160hr5gmpo=0x0 +sb40and80hr5gmpo=0x0 +sb20in80and160hr5ghpo=0x0 +sb40and80hr5ghpo=0x0 +sb20in40lrpo=0x0 +sb20in80and160lr5glpo=0x0 +sb40and80lr5glpo=0x0 +sb20in80and160lr5gmpo=0x0 +sb40and80lr5gmpo=0x0 +sb20in80and160lr5ghpo=0x0 +sb40and80lr5ghpo=0x0 +dot11agduphrpo=0x0 +dot11agduplrpo=0x0 +phycal_tempdelta=25 +cckdigfilttype=2 +pacalidx2g=65 +dacrate2g=160 +swctrlmap_5g=0x00000008,0x00000010,0x00000008,0x000000,0x038 +swctrlmap_2g=0x00000001,0x00000002,0x00000001,0x040002,0x0ff +swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +rssicorrnorm_c0=3,3 +rssicorrnorm5g_c0=2,3,4,2,3,3,0,1,2,0,1,2 +muxenab=0x10 diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/files/imx6ul-pico/brcmfmac4339-sdio.txt b/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/files/imx6ul-pico/brcmfmac4339-sdio.txt new file mode 100644 index 00000000..1ddd9295 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/broadcom-nvram-config/files/imx6ul-pico/brcmfmac4339-sdio.txt @@ -0,0 +1,99 @@ +#AP6335_NVRAM_V1.5_03112014 +NVRAMRev=$Rev: 410316 $ +sromrev=11 +boardrev=0x1203 +boardtype=0x06c5 +boardflags=0x00000c01 +boardflags2=0x00002000 +boardflags3=0x101188 +macaddr=00:90:4c:c5:12:38 +ccode=0 +regrev=0 +antswitch=0 +pdgain2g=7 +pdgain5g=7 +tworangetssi2g=0 +tworangetssi5g=0 +femctrl=7 +pcieingress_war=15 +vendid=0x14e4 +devid=0x43ae +manfid=0x2d0 +nocrc=1 +otpimagesize=502 +xtalfreq=37400 +extpagain2g=2 +pdetrange2g=2 +extpagain5g=2 +pdetrange5g=2 +rxgains2gelnagaina0=0 +rxgains2gtrisoa0=7 +rxgains2gtrelnabypa0=0 +rxgains5gelnagaina0=0 +rxgains5gtrisoa0=11 +rxgains5gtrelnabypa0=0 +rxchain=1 +txchain=1 +aa2g=1 +aa5g=1 +tssipos5g=0 +tssipos2g=0 +pa2ga0=-161,6269,-723 +pa2gccka0=-116,7568,-852 +pa5ga0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pa5gbw40a0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pa5gbw80a0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pdoffset40ma0=0 +pdoffset80ma0=0 +pdoffsetcckma0=0 +maxp2ga0=75 +maxp5ga0=64,64,72,72 +cckbw202gpo=0x0000 +cckbw20ul2gpo=0x0 +mcsbw202gpo=0x99445533 +mcsbw402gpo=0x99775533 +dot11agofdmhrbw202gpo=0x2233 +ofdmlrbw202gpo=0x0000 +tssifloor2g=500 +mcsbw205glpo=0x66333330 +mcsbw405glpo=0x66665530 +mcsbw805glpo=0xAA555530 +mcsbw1605glpo=0x99555530 +mcsbw205gmpo=0x99BB5530 +mcsbw405gmpo=0x99BB5530 +mcsbw805gmpo=0xEE555530 +mcsbw1605gmpo=0x99555530 +mcsbw205ghpo=0x99995530 +mcsbw405ghpo=0x99BB5530 +mcsbw805ghpo=0xEE555530 +mcsbw1605ghpo=0x99555530 +mcslr5glpo=0x0000 +mcslr5gmpo=0x0000 +mcslr5ghpo=0x0000 +sb20in40hrrpo=0x0 +sb20in80and160hr5glpo=0x0 +sb40and80hr5glpo=0x0 +sb20in80and160hr5gmpo=0x0 +sb40and80hr5gmpo=0x0 +sb20in80and160hr5ghpo=0x0 +sb40and80hr5ghpo=0x0 +sb20in40lrpo=0x0 +sb20in80and160lr5glpo=0x0 +sb40and80lr5glpo=0x0 +sb20in80and160lr5gmpo=0x0 +sb40and80lr5gmpo=0x0 +sb20in80and160lr5ghpo=0x0 +sb40and80lr5ghpo=0x0 +dot11agduphrpo=0x0 +dot11agduplrpo=0x0 +phycal_tempdelta=25 +cckdigfilttype=2 +pacalidx2g=65 +dacrate2g=160 +swctrlmap_5g=0x00000008,0x00000010,0x00000008,0x000000,0x038 +swctrlmap_2g=0x00000001,0x00000002,0x00000001,0x040002,0x0ff +swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +rssicorrnorm_c0=3,3 +rssicorrnorm5g_c0=2,3,4,2,3,3,0,1,2,0,1,2 +muxenab=0x10 diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/imx-atf/imx-atf-boundary_2.3.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/imx-atf/imx-atf-boundary_2.3.bb new file mode 100644 index 00000000..93662466 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/imx-atf/imx-atf-boundary_2.3.bb @@ -0,0 +1,56 @@ +# Copyright (C) 2017-2019 NXP + +DESCRIPTION = "i.MX ARM Trusted Firmware" +SECTION = "BSP" +LICENSE = "BSD-3-Clause" +LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/BSD-3-Clause;md5=550794465ba0ec5312d6919e203a55f9" + +PROVIDES = "imx-atf" + +PV .= "+git${SRCPV}" + +SRCBRANCH = "boundary-imx_4.14.98_2.3.0" +SRC_URI = "git://github.com/boundarydevices/imx-atf.git;branch=${SRCBRANCH} \ +" +SRCREV = "99e07a29006b35e5b76e3a2555c54575f3b63d0c" + +S = "${WORKDIR}/git" + +inherit deploy + +BOOT_TOOLS = "imx-boot-tools" + +PLATFORM ?= "INVALID" +PLATFORM_mx8mq = "imx8mq" +PLATFORM_mx8mm = "imx8mm" +PLATFORM_mx8mn = "imx8mn" + +EXTRA_OEMAKE += " \ + CROSS_COMPILE="${TARGET_PREFIX}" \ + PLAT=${PLATFORM} \ +" + +BUILD_OPTEE = "${@bb.utils.contains('MACHINE_FEATURES', 'optee', 'true', 'false', d)}" + +do_compile() { + # Clear LDFLAGS to avoid the option -Wl recognize issue + unset LDFLAGS + oe_runmake bl31 + if ${BUILD_OPTEE}; then + oe_runmake clean BUILD_BASE=build-optee + oe_runmake BUILD_BASE=build-optee SPD=opteed bl31 + fi +} + +do_install[noexec] = "1" + +do_deploy() { + install -Dm 0644 ${S}/build/${PLATFORM}/release/bl31.bin ${DEPLOYDIR}/${BOOT_TOOLS}/bl31-${PLATFORM}.bin + if ${BUILD_OPTEE}; then + install -m 0644 ${S}/build-optee/${PLATFORM}/release/bl31.bin ${DEPLOYDIR}/${BOOT_TOOLS}/bl31-${PLATFORM}.bin-optee + fi +} +addtask deploy after do_compile + +PACKAGE_ARCH = "${MACHINE_SOCARCH}" +COMPATIBLE_MACHINE = "(nitrogen8m|nitrogen8mm|nitrogen8mn)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/libmcc2/libmcc2_2.0.1.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/libmcc2/libmcc2_2.0.1.bb deleted file mode 100644 index ce49b8b4..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/libmcc2/libmcc2_2.0.1.bb +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (C) 2013 Timesys Corporation -SUMMARY = "Multicore communication Library" -LICENSE = "GPL-2.0 | BSD" -LIC_FILES_CHKSUM = "file://LICENSE;md5=c49712341497d0b5f2e40c30dff2af9d \ - file://BSD_LICENSE;md5=10695b8f86532e5e44640acf4d92a2ef" - -DEPENDS = "virtual/kernel-module-mcc" - -SRC_URI = "http://repository.timesys.com/buildsources/l/libmcc2/libmcc2-${PV}/libmcc2-${PV}.tar.bz2" - -SRC_URI[md5sum] = "bd47714eb44ad67915ed51994e3af096" -SRC_URI[sha256sum] = "3bcbd9f3092c3be6edc6ab725346e822f05f303ce1dc5482fb320f4a1754f52d" - -S = "${WORKDIR}/libmcc2-${PV}" - -CFLAGS += "-I${STAGING_KERNEL_DIR}/include/uapi" - -RDEPENDS_${PN} = "virtual/kernel-module-mcc" - -COMPATIBLE_MACHINE = "(vf60)" - -do_install() { - oe_runmake 'DESTDIR=${D}' install -} - -RDEPENDS_${PN}-dev += "virtual/kernel-module-mcc-dev" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/mc-utils/mc-utils-lx2160acex7/0001-lx2160acex7-add-8x10G-dual-40G-and-dual-100G-DPL-DPC.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/mc-utils/mc-utils-lx2160acex7/0001-lx2160acex7-add-8x10G-dual-40G-and-dual-100G-DPL-DPC.patch new file mode 100644 index 00000000..b4f94f8c --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/mc-utils/mc-utils-lx2160acex7/0001-lx2160acex7-add-8x10G-dual-40G-and-dual-100G-DPL-DPC.patch @@ -0,0 +1,1912 @@ +From 1b1279d4ce8eb28a3c4f1e98bcd62f16173d8285 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 14:40:28 +0300 +Subject: [PATCH] lx2160acex7: add 8x10G, dual 40G and dual 100G DPL/DPC files + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + config/lx2160a/CEX7/dpc-8_x_usxgmii.dts | 103 ++++ + config/lx2160a/CEX7/dpc-dual-100g.dts | 85 +++ + config/lx2160a/CEX7/dpc-dual-40g.dts | 85 +++ + config/lx2160a/CEX7/dpl-eth.8x10g.19.dts | 532 ++++++++++++++++++ + config/lx2160a/CEX7/dpl-eth.dual-100g.19.dts | 511 ++++++++++++++++++ + config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts | 534 +++++++++++++++++++ + 6 files changed, 1850 insertions(+) + create mode 100644 config/lx2160a/CEX7/dpc-8_x_usxgmii.dts + create mode 100644 config/lx2160a/CEX7/dpc-dual-100g.dts + create mode 100644 config/lx2160a/CEX7/dpc-dual-40g.dts + create mode 100644 config/lx2160a/CEX7/dpl-eth.8x10g.19.dts + create mode 100644 config/lx2160a/CEX7/dpl-eth.dual-100g.19.dts + create mode 100644 config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts + +diff --git a/config/lx2160a/CEX7/dpc-8_x_usxgmii.dts b/config/lx2160a/CEX7/dpc-8_x_usxgmii.dts +new file mode 100644 +index 0000000..44e22bb +--- /dev/null ++++ b/config/lx2160a/CEX7/dpc-8_x_usxgmii.dts +@@ -0,0 +1,103 @@ ++/* ++* Copyright 2018 NXP ++* ++* Redistribution and use in source and binary forms, with or without ++* modification, are permitted provided that the following conditions are met: ++* * Redistributions of source code must retain the above copyright ++* notice, this list of conditions and the following disclaimer. ++* * Redistributions in binary form must reproduce the above copyright ++* notice, this list of conditions and the following disclaimer in the ++* documentation and/or other materials provided with the distribution. ++* * Neither the name of the above-listed copyright holders nor the ++* names of any contributors may be used to endorse or promote products ++* derived from this software without specific prior written permission. ++* ++* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++* POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* ++* This DPC showcases one Linux configuration for lx2160a boards. ++*/ ++ ++/dts-v1/; ++ ++/ { ++ ++ resources { ++ ++ icid_pools { ++ ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <32>; ++ }; ++ }; ++ ++ board_info { ++ ports { ++ mac@3 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@4 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@5 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@6 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@7 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@8 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@9 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@10 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2160a/CEX7/dpc-dual-100g.dts b/config/lx2160a/CEX7/dpc-dual-100g.dts +new file mode 100644 +index 0000000..0601a07 +--- /dev/null ++++ b/config/lx2160a/CEX7/dpc-dual-100g.dts +@@ -0,0 +1,85 @@ ++/* ++* Copyright 2018 NXP ++* ++* Redistribution and use in source and binary forms, with or without ++* modification, are permitted provided that the following conditions are met: ++* * Redistributions of source code must retain the above copyright ++* notice, this list of conditions and the following disclaimer. ++* * Redistributions in binary form must reproduce the above copyright ++* notice, this list of conditions and the following disclaimer in the ++* documentation and/or other materials provided with the distribution. ++* * Neither the name of the above-listed copyright holders nor the ++* names of any contributors may be used to endorse or promote products ++* derived from this software without specific prior written permission. ++* ++* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++* POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* ++* This DPC showcases one Linux configuration for lx2160a boards. ++*/ ++ ++/dts-v1/; ++ ++/ { ++ ++ resources { ++ ++ icid_pools { ++ ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <32>; ++ }; ++ }; ++ ++ board_info { ++ ports { ++ mac@1 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@2 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2160a/CEX7/dpc-dual-40g.dts b/config/lx2160a/CEX7/dpc-dual-40g.dts +new file mode 100644 +index 0000000..0601a07 +--- /dev/null ++++ b/config/lx2160a/CEX7/dpc-dual-40g.dts +@@ -0,0 +1,85 @@ ++/* ++* Copyright 2018 NXP ++* ++* Redistribution and use in source and binary forms, with or without ++* modification, are permitted provided that the following conditions are met: ++* * Redistributions of source code must retain the above copyright ++* notice, this list of conditions and the following disclaimer. ++* * Redistributions in binary form must reproduce the above copyright ++* notice, this list of conditions and the following disclaimer in the ++* documentation and/or other materials provided with the distribution. ++* * Neither the name of the above-listed copyright holders nor the ++* names of any contributors may be used to endorse or promote products ++* derived from this software without specific prior written permission. ++* ++* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++* POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* ++* This DPC showcases one Linux configuration for lx2160a boards. ++*/ ++ ++/dts-v1/; ++ ++/ { ++ ++ resources { ++ ++ icid_pools { ++ ++ icid_pool@1 { ++ num = <0x64>; ++ base_icid = <0x0>; ++ }; ++ }; ++ }; ++ ++ mc_general { ++ ++ log { ++ mode = "LOG_MODE_ON"; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ ++ console { ++ mode = "CONSOLE_MODE_OFF"; ++ uart_id = <0x4>; ++ level = "LOG_LEVEL_WARNING"; ++ }; ++ }; ++ ++ controllers { ++ ++ qbman { ++ /* Transform this number of 8-WQ channels into four times ++ * as many 2-WQ channels. This allows the creation of a ++ * larger number of DPCONs. ++ */ ++ wq_ch_conversion = <32>; ++ }; ++ }; ++ ++ board_info { ++ ports { ++ mac@1 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@2 { ++ link_type = "MAC_LINK_TYPE_FIXED"; ++ }; ++ mac@17 { ++ link_type = "MAC_LINK_TYPE_PHY"; ++ }; ++ }; ++ }; ++}; +diff --git a/config/lx2160a/CEX7/dpl-eth.8x10g.19.dts b/config/lx2160a/CEX7/dpl-eth.8x10g.19.dts +new file mode 100644 +index 0000000..b72af03 +--- /dev/null ++++ b/config/lx2160a/CEX7/dpl-eth.8x10g.19.dts +@@ -0,0 +1,532 @@ ++/* ++ * Copyright 2018 NXP ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ dpl-version = <0xa>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ dprc@1 { ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ objects { ++ /* ------------ DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0x0>; ++ }; ++ ++ ++ /* ------------ DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0x11>; ++ }; ++ ++ ++ /* ------------ DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0x0 0x1>; ++ }; ++ ++ /* ------------ DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>; ++ }; ++ ++ /* ------------ DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; ++ }; ++ ++ /* ------------ DPCON --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; ++ }; ++ ++ /* ------------ DPSECI --------------*/ ++ obj@700 { ++ obj_name = "dpseci@0"; ++ }; ++ ++ /* ------------ DPRTC --------------*/ ++ obj@800 { ++ obj_name="dprtc@0"; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ /* ------------ DPNI --------------*/ ++ dpni@0 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@1 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@2 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@3 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@4 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@5 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@6 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@7 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@8 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpmac@2 { ++ }; ++ ++ dpmac@3 { ++ }; ++ ++ dpmac@4 { ++ }; ++ ++ dpmac@5 { ++ }; ++ ++ dpmac@6 { ++ }; ++ dpmac@7 { ++ }; ++ dpmac@8 { ++ }; ++ dpmac@9 { ++ }; ++ dpmac@10 { ++ }; ++ ++ dpmac@17 { ++ }; ++ ++ dpmac@18 { ++ }; ++ ++ /* ------------ DPBP --------------*/ ++ dpbp@0 { ++ }; ++ ++ dpbp@1 { ++ }; ++ ++ ++ /* ------------ DPIO --------------*/ ++ dpio@0 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ /* ------------ DPMCP --------------*/ ++ dpmcp@1 { ++ }; ++ ++ dpmcp@2 { ++ }; ++ ++ dpmcp@3 { ++ }; ++ ++ dpmcp@4 { ++ }; ++ ++ dpmcp@5 { ++ }; ++ ++ dpmcp@6 { ++ }; ++ ++ dpmcp@7 { ++ }; ++ ++ dpmcp@8 { ++ }; ++ ++ dpmcp@9 { ++ }; ++ ++ dpmcp@10 { ++ }; ++ ++ dpmcp@11 { ++ }; ++ ++ dpmcp@12 { ++ }; ++ ++ dpmcp@13 { ++ }; ++ ++ dpmcp@14 { ++ }; ++ ++ dpmcp@15 { ++ }; ++ ++ dpmcp@16 { ++ }; ++ ++ dpmcp@17 { ++ }; ++ ++ dpmcp@18 { ++ }; ++ ++ dpmcp@19 { ++ }; ++ ++ dpmcp@20 { ++ }; ++ ++ dpmcp@21 { ++ }; ++ ++ dpmcp@22 { ++ }; ++ ++ dpmcp@23 { ++ }; ++ ++ dpmcp@24 { ++ }; ++ ++ dpmcp@25 { ++ }; ++ ++ dpmcp@26 { ++ }; ++ ++ dpmcp@27 { ++ }; ++ ++ dpmcp@28 { ++ }; ++ ++ dpmcp@29 { ++ }; ++ ++ dpmcp@30 { ++ }; ++ ++ dpmcp@31 { ++ }; ++ ++ dpmcp@32 { ++ }; ++ ++ dpmcp@33 { ++ }; ++ ++ dpmcp@34 { ++ }; ++ ++ dpmcp@35 { ++ }; ++ ++ /* ------------ DPCON --------------*/ ++ dpcon@0 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ num_priorities = <0x2>; ++ }; ++ dpcon@16 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ num_priorities = <0x2>; ++ }; ++ ++ /* ------------ DPSECI --------------*/ ++ dpseci@0 { ++ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>; ++ options = "DPSECI_OPT_HAS_CG"; ++ }; ++ ++ /* ------------ DPRTC --------------*/ ++ dprtc@0 { ++ compatible="fsl,dprtc"; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ connection@1 { ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@17"; ++ }; ++/* connection@2 { ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@3"; ++ }; ++ connection@3 { ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@4"; ++ }; ++ connection@4 { ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@5"; ++ }; ++ connection@5 { ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@6"; ++ };*/ ++ }; ++}; ++ +diff --git a/config/lx2160a/CEX7/dpl-eth.dual-100g.19.dts b/config/lx2160a/CEX7/dpl-eth.dual-100g.19.dts +new file mode 100644 +index 0000000..bb1b54f +--- /dev/null ++++ b/config/lx2160a/CEX7/dpl-eth.dual-100g.19.dts +@@ -0,0 +1,511 @@ ++/* ++ * Copyright 2018 NXP ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ dpl-version = <0xa>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ dprc@1 { ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ objects { ++ /* ------------ DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0x0>; ++ }; ++ ++ ++ /* ------------ DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <0x1 0x2 0x11>; ++ }; ++ ++ ++ /* ------------ DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0x0 0x1>; ++ }; ++ ++ /* ------------ DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>; ++ }; ++ ++ /* ------------ DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; ++ }; ++ ++ /* ------------ DPCON --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; ++ }; ++ ++ /* ------------ DPSECI --------------*/ ++ obj@700 { ++ obj_name = "dpseci@0"; ++ }; ++ ++ /* ------------ DPRTC --------------*/ ++ obj@800 { ++ obj_name="dprtc@0"; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ /* ------------ DPNI --------------*/ ++ dpni@0 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@1 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@2 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@3 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@4 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@5 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@6 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@7 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@8 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpmac@1 { ++ }; ++ dpmac@2 { ++ }; ++ ++ dpmac@17 { ++ }; ++ ++ /* ------------ DPBP --------------*/ ++ dpbp@0 { ++ }; ++ ++ dpbp@1 { ++ }; ++ ++ ++ /* ------------ DPIO --------------*/ ++ dpio@0 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ /* ------------ DPMCP --------------*/ ++ dpmcp@1 { ++ }; ++ ++ dpmcp@2 { ++ }; ++ ++ dpmcp@3 { ++ }; ++ ++ dpmcp@4 { ++ }; ++ ++ dpmcp@5 { ++ }; ++ ++ dpmcp@6 { ++ }; ++ ++ dpmcp@7 { ++ }; ++ ++ dpmcp@8 { ++ }; ++ ++ dpmcp@9 { ++ }; ++ ++ dpmcp@10 { ++ }; ++ ++ dpmcp@11 { ++ }; ++ ++ dpmcp@12 { ++ }; ++ ++ dpmcp@13 { ++ }; ++ ++ dpmcp@14 { ++ }; ++ ++ dpmcp@15 { ++ }; ++ ++ dpmcp@16 { ++ }; ++ ++ dpmcp@17 { ++ }; ++ ++ dpmcp@18 { ++ }; ++ ++ dpmcp@19 { ++ }; ++ ++ dpmcp@20 { ++ }; ++ ++ dpmcp@21 { ++ }; ++ ++ dpmcp@22 { ++ }; ++ ++ dpmcp@23 { ++ }; ++ ++ dpmcp@24 { ++ }; ++ ++ dpmcp@25 { ++ }; ++ ++ dpmcp@26 { ++ }; ++ ++ dpmcp@27 { ++ }; ++ ++ dpmcp@28 { ++ }; ++ ++ dpmcp@29 { ++ }; ++ ++ dpmcp@30 { ++ }; ++ ++ dpmcp@31 { ++ }; ++ ++ dpmcp@32 { ++ }; ++ ++ dpmcp@33 { ++ }; ++ ++ dpmcp@34 { ++ }; ++ ++ dpmcp@35 { ++ }; ++ ++ /* ------------ DPCON --------------*/ ++ dpcon@0 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ num_priorities = <0x2>; ++ }; ++ dpcon@16 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ num_priorities = <0x2>; ++ }; ++ ++ /* ------------ DPSECI --------------*/ ++ dpseci@0 { ++ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>; ++ options = "DPSECI_OPT_HAS_CG"; ++ }; ++ ++ /* ------------ DPRTC --------------*/ ++ dprtc@0 { ++ compatible="fsl,dprtc"; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ connection@1 { ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@17"; ++ }; ++/* connection@2 { ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@3"; ++ }; ++ connection@3 { ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@4"; ++ }; ++ connection@4 { ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@5"; ++ }; ++ connection@5 { ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@6"; ++ };*/ ++ }; ++}; ++ +diff --git a/config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts b/config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts +new file mode 100644 +index 0000000..5619fd2 +--- /dev/null ++++ b/config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts +@@ -0,0 +1,534 @@ ++/* ++ * Copyright 2018 NXP ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ dpl-version = <0xa>; ++ /***************************************************************** ++ * Containers ++ *****************************************************************/ ++ containers { ++ dprc@1 { ++ parent = "none"; ++ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED"; ++ objects { ++ /* ------------ DPNIs --------------*/ ++ obj_set@dpni { ++ type = "dpni"; ++ ids = <0x0>; ++ }; ++ ++ ++ /* ------------ DPMACs --------------*/ ++ obj_set@dpmac { ++ type = "dpmac"; ++ ids = <0x1 0x2 0x11>; ++ }; ++ ++ ++ /* ------------ DPBPs --------------*/ ++ obj_set@dpbp { ++ type = "dpbp"; ++ ids = <0x0 0x1>; ++ }; ++ ++ /* ------------ DPIOs --------------*/ ++ obj_set@dpio { ++ type = "dpio"; ++ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>; ++ }; ++ ++ /* ------------ DPMCPs --------------*/ ++ obj_set@dpmcp { ++ type = "dpmcp"; ++ ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; ++ }; ++ ++ /* ------------ DPCON --------------*/ ++ obj_set@dpcon { ++ type = "dpcon"; ++ ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; ++ }; ++ ++ /* ------------ DPSECI --------------*/ ++ obj@700 { ++ obj_name = "dpseci@0"; ++ }; ++ ++ /* ------------ DPRTC --------------*/ ++ obj@800 { ++ obj_name="dprtc@0"; ++ }; ++ }; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Objects ++ *****************************************************************/ ++ objects { ++ ++ /* ------------ DPNI --------------*/ ++ dpni@0 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@1 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@2 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@3 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@4 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@5 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@6 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@7 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpni@8 { ++ options = "DPNI_OPT_HAS_KEY_MASKING"; ++ num_queues = <0x10>; ++ num_tcs = <0x1>; ++ }; ++ dpmac@1 { ++ }; ++ dpmac@2 { ++ }; ++ ++ dpmac@3 { ++ }; ++ ++ dpmac@4 { ++ }; ++ ++ dpmac@5 { ++ }; ++ ++ dpmac@6 { ++ }; ++ dpmac@7 { ++ }; ++ dpmac@8 { ++ }; ++ dpmac@9 { ++ }; ++ dpmac@10 { ++ }; ++ ++ dpmac@17 { ++ }; ++ ++ dpmac@18 { ++ }; ++ ++ /* ------------ DPBP --------------*/ ++ dpbp@0 { ++ }; ++ ++ dpbp@1 { ++ }; ++ ++ ++ /* ------------ DPIO --------------*/ ++ dpio@0 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@1 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@2 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@3 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@4 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@5 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@6 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@7 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@8 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@9 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@10 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@11 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@12 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@13 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@14 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ dpio@15 { ++ channel_mode = "DPIO_LOCAL_CHANNEL"; ++ num_priorities = <0x8>; ++ }; ++ ++ /* ------------ DPMCP --------------*/ ++ dpmcp@1 { ++ }; ++ ++ dpmcp@2 { ++ }; ++ ++ dpmcp@3 { ++ }; ++ ++ dpmcp@4 { ++ }; ++ ++ dpmcp@5 { ++ }; ++ ++ dpmcp@6 { ++ }; ++ ++ dpmcp@7 { ++ }; ++ ++ dpmcp@8 { ++ }; ++ ++ dpmcp@9 { ++ }; ++ ++ dpmcp@10 { ++ }; ++ ++ dpmcp@11 { ++ }; ++ ++ dpmcp@12 { ++ }; ++ ++ dpmcp@13 { ++ }; ++ ++ dpmcp@14 { ++ }; ++ ++ dpmcp@15 { ++ }; ++ ++ dpmcp@16 { ++ }; ++ ++ dpmcp@17 { ++ }; ++ ++ dpmcp@18 { ++ }; ++ ++ dpmcp@19 { ++ }; ++ ++ dpmcp@20 { ++ }; ++ ++ dpmcp@21 { ++ }; ++ ++ dpmcp@22 { ++ }; ++ ++ dpmcp@23 { ++ }; ++ ++ dpmcp@24 { ++ }; ++ ++ dpmcp@25 { ++ }; ++ ++ dpmcp@26 { ++ }; ++ ++ dpmcp@27 { ++ }; ++ ++ dpmcp@28 { ++ }; ++ ++ dpmcp@29 { ++ }; ++ ++ dpmcp@30 { ++ }; ++ ++ dpmcp@31 { ++ }; ++ ++ dpmcp@32 { ++ }; ++ ++ dpmcp@33 { ++ }; ++ ++ dpmcp@34 { ++ }; ++ ++ dpmcp@35 { ++ }; ++ ++ /* ------------ DPCON --------------*/ ++ dpcon@0 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@1 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@2 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@3 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@4 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@5 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@6 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@7 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@8 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@9 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@10 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@11 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@12 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@13 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@14 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@15 { ++ num_priorities = <0x2>; ++ }; ++ dpcon@16 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@17 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@18 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@19 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@20 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@21 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@22 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@23 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@24 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@25 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@26 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@27 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@28 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@29 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@30 { ++ num_priorities = <0x2>; ++ }; ++ ++ dpcon@31 { ++ num_priorities = <0x2>; ++ }; ++ ++ /* ------------ DPSECI --------------*/ ++ dpseci@0 { ++ priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>; ++ options = "DPSECI_OPT_HAS_CG"; ++ }; ++ ++ /* ------------ DPRTC --------------*/ ++ dprtc@0 { ++ compatible="fsl,dprtc"; ++ }; ++ }; ++ ++ /***************************************************************** ++ * Connections ++ *****************************************************************/ ++ connections { ++ connection@1 { ++ endpoint1 = "dpni@0"; ++ endpoint2 = "dpmac@17"; ++ }; ++/* connection@2 { ++ endpoint1 = "dpni@1"; ++ endpoint2 = "dpmac@3"; ++ }; ++ connection@3 { ++ endpoint1 = "dpni@2"; ++ endpoint2 = "dpmac@4"; ++ }; ++ connection@4 { ++ endpoint1 = "dpni@3"; ++ endpoint2 = "dpmac@5"; ++ }; ++ connection@5 { ++ endpoint1 = "dpni@4"; ++ endpoint2 = "dpmac@6"; ++ };*/ ++ }; ++}; ++ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/mc-utils/mc-utils_git.bbappend b/bsp/meta-freescale-3rdparty/recipes-bsp/mc-utils/mc-utils_git.bbappend new file mode 100644 index 00000000..09c04156 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/mc-utils/mc-utils_git.bbappend @@ -0,0 +1,7 @@ +FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:" + +SRC_URI_append_lx2160acex7 = "\ + file://0001-lx2160acex7-add-8x10G-dual-40G-and-dual-100G-DPL-DPC.patch \ +" + +MC_FLAVOUR_lx2160acex7 = "CEX7" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0001-lx2160acex7-misc-RCW-files.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0001-lx2160acex7-misc-RCW-files.patch new file mode 100644 index 00000000..ae873990 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0001-lx2160acex7-misc-RCW-files.patch @@ -0,0 +1,640 @@ +From ef5ab1b5a7262a6ef9caf334b0c772b0ebf00fdf Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 14:43:06 +0300 +Subject: [PATCH] lx2160acex7 misc RCW files + +This patch adds support for lx2160a rcw project. +In general RCW has lots of redundent files and can be restructured +better as in this patch. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/Makefile | 2 + + lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig | 61 +++++++++++++++++++ + .../rcw_1900_600_2600_17_4_2.rcw | 4 ++ + .../rcw_1900_600_2600_17_4_2_sd.rcw | 4 ++ + .../rcw_2000_700_2400_13_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2400_20_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2400_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2600_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2900_17_4_2_sd.rcw | 4 ++ + .../rcw_2000_700_2900_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_17_4_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_20_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_8_5_0_sd.rcw | 4 ++ + .../rcw_2000_700_3200_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_8_5_2_xspi.rcw | 4 ++ + .../rcw_2400_700_3200_8_5_2_sd.rcw | 4 ++ + .../rcw_2500_700_3200_8_5_2_sd.rcw | 4 ++ + .../rcw_2600_700_3200_8_5_2_sd.rcw | 4 ++ + .../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw | 4 ++ + lx2160acex7/configs/lx2160a_13_5_2.rcwi | 3 + + lx2160acex7/configs/lx2160a_17_4_2.rcwi | 7 +++ + .../configs/lx2160a_1900_600_2600.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_2400.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_2600.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_2900.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_3200.rcwi | 12 ++++ + lx2160acex7/configs/lx2160a_20_5_2.rcwi | 7 +++ + .../configs/lx2160a_2400_700_3200.rcwi | 12 ++++ + .../configs/lx2160a_2500_700_3200.rcwi | 12 ++++ + .../configs/lx2160a_2600_700_3200.rcwi | 12 ++++ + lx2160acex7/configs/lx2160a_8_5_0.rcwi | 7 +++ + lx2160acex7/configs/lx2160a_8_5_2.rcwi | 7 +++ + lx2160acex7/configs/lx2160a_defaults.rcwi | 19 ++++++ + lx2160acex7/configs/lx2160a_sdboot.rcwi | 20 ++++++ + lx2160acex7/configs/lx2160a_test.rcwi | 20 ++++++ + lx2160acex7/configs/lx2160a_xspiboot.rcwi | 17 ++++++ + 36 files changed, 334 insertions(+) + create mode 100644 lx2160acex7/Makefile + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw + create mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_1900_600_2600.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2400.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2600.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2900.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_20_5_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2400_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2500_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2600_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_8_5_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_defaults.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_sdboot.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_test.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_xspiboot.rcwi + +diff --git a/lx2160acex7/Makefile b/lx2160acex7/Makefile +new file mode 100644 +index 0000000..d7e9447 +--- /dev/null ++++ b/lx2160acex7/Makefile +@@ -0,0 +1,2 @@ ++include ../Makefile.inc ++ +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig +new file mode 100644 +index 0000000..cdb6446 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig +@@ -0,0 +1,61 @@ ++/* ++ * SerDes Protocol 1 - 19 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 1900 MHz ++ * Platform -- 600 MHz ++ * DDR -- 2600 MT/s ++ */ ++ ++#include <../lx2160asi/lx2160a.rcwi> ++ ++SYS_PLL_RAT=12 ++MEM_PLL_CFG=3 ++MEM_PLL_RAT=26 ++MEM2_PLL_CFG=3 ++MEM2_PLL_RAT=26 ++CGA_PLL1_RAT=19 ++CGA_PLL2_RAT=19 ++CGB_PLL1_RAT=19 ++CGB_PLL2_RAT=9 ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++HWA_CGA_M1_CLK_SEL=1 ++HWA_CGB_M1_CLK_SEL=7 ++BOOT_LOC=26 ++SYSCLK_FREQ=600 ++IIC2_PMUX=6 ++IIC3_PMUX=2 ++IIC4_PMUX=2 ++USB3_CLK_FSEL=39 ++SRDS_PRTCL_S1=19 ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_DIV_PEX_S1=1 ++SRDS_DIV_PEX_S2=3 ++SRDS_DIV_PEX_S3=1 ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Copy SPL Uboot to Ocram */ ++.pbi ++blockcopy 0x08,0x00100000,0x1800a000,0x00020000 ++.end ++ ++/* Boot Location Pointer */ ++#include <../lx2160asi/bootlocptr_sd.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_24.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw +new file mode 100644 +index 0000000..13ab0b9 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_1900_600_2600.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw +new file mode 100644 +index 0000000..14fae8c +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_1900_600_2600.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw +new file mode 100644 +index 0000000..2dae5a2 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2400.rcwi> ++#include <configs/lx2160a_13_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw +new file mode 100644 +index 0000000..5335072 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2400.rcwi> ++#include <configs/lx2160a_20_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw +new file mode 100644 +index 0000000..e2a5bd3 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2400.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw +new file mode 100644 +index 0000000..a330bfe +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2600.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw +new file mode 100644 +index 0000000..8535dbd +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2900.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw +new file mode 100644 +index 0000000..698be01 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2900.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw +new file mode 100644 +index 0000000..780d8c3 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw +new file mode 100644 +index 0000000..eb9d240 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_20_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw +new file mode 100644 +index 0000000..ceb53a3 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_8_5_0.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..a220e98 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..1eabd7d +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..2ac59b1 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2400_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..e7c08df +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2500_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..1e7a8f7 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2600_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw +new file mode 100644 +index 0000000..86f12f8 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_test.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi +new file mode 100644 +index 0000000..76f44bc +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_13_5_2.rcwi +@@ -0,0 +1,3 @@ ++SRDS_PRTCL_S1=13 ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 +diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi +new file mode 100644 +index 0000000..358972d +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_17_4_2.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=17 ++SRDS_PRTCL_S2=4 ++SRDS_PRTCL_S3=2 ++ ++/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */ ++/*SRDS_PLL_REF_CLK_SEL_S1=2*/ ++ +diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi +new file mode 100644 +index 0000000..8b61021 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=19 ++CGA_PLL2_RAT=19 ++CGB_PLL1_RAT=19 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=12 ++ ++MEM_PLL_RAT=26 ++MEM2_PLL_RAT=26 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi +new file mode 100644 +index 0000000..6b0b150 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=24 ++MEM2_PLL_RAT=24 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi +new file mode 100644 +index 0000000..21dce67 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=26 ++MEM2_PLL_RAT=26 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi +new file mode 100644 +index 0000000..e6a8e30 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=29 ++MEM2_PLL_RAT=29 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi +new file mode 100644 +index 0000000..27ee377 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_20_5_2.rcwi +new file mode 100644 +index 0000000..c2c7bea +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_20_5_2.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=20 ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 ++ ++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */ ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_PLL_PD_PLL1=1 +diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi +new file mode 100644 +index 0000000..fc0fd6c +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=24 ++CGA_PLL2_RAT=24 ++CGB_PLL1_RAT=24 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi +new file mode 100644 +index 0000000..62d9069 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=25 ++CGA_PLL2_RAT=25 ++CGB_PLL1_RAT=25 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi +new file mode 100644 +index 0000000..e244917 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=26 ++CGA_PLL2_RAT=26 ++CGB_PLL1_RAT=26 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi +new file mode 100644 +index 0000000..62ff153 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_8_5_0.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=8 /* should be 8 */ ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=0 ++ ++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */ ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_PLL_PD_PLL1=1 +diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_8_5_2.rcwi +new file mode 100644 +index 0000000..d7d707a +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_8_5_2.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=8 /* should be 8 */ ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 ++ ++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */ ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_PLL_PD_PLL1=1 +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +new file mode 100644 +index 0000000..6fd65ec +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -0,0 +1,19 @@ ++#include <../lx2160asi/lx2160a.rcwi> ++MEM_PLL_CFG=3 ++MEM2_PLL_CFG=3 ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++HWA_CGA_M1_CLK_SEL=1 ++HWA_CGB_M1_CLK_SEL=7 ++BOOT_LOC=26 ++SYSCLK_FREQ=600 ++IIC2_PMUX=6 ++IIC3_PMUX=0 ++IIC4_PMUX=2 ++USB3_CLK_FSEL=39 ++SRDS_DIV_PEX_S1=1 ++SRDS_DIV_PEX_S2=3 ++SRDS_DIV_PEX_S3=1 ++ +diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi +new file mode 100644 +index 0000000..d537ea5 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi +@@ -0,0 +1,20 @@ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Copy SPL Uboot to Ocram */ ++.pbi ++blockcopy 0x08,0x00100000,0x1800a000,0x00020000 ++.end ++ ++/* Boot Location Pointer */ ++#include <../lx2160asi/bootlocptr_sd.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Errata for PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ +diff --git a/lx2160acex7/configs/lx2160a_test.rcwi b/lx2160acex7/configs/lx2160a_test.rcwi +new file mode 100644 +index 0000000..a223be1 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_test.rcwi +@@ -0,0 +1,20 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=8 ++ ++SYS_PLL_RAT=12 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_24.rcw> */ ++ ++SRDS_PLL_PD_PLL1=1 ++SRDS_PLL_PD_PLL2=1 ++SRDS_PLL_PD_PLL3=1 ++SRDS_PLL_PD_PLL4=1 ++SRDS_PLL_PD_PLL5=1 ++SRDS_PLL_PD_PLL6=1 ++ +diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +new file mode 100644 +index 0000000..eecc314 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +@@ -0,0 +1,17 @@ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Boot Location Pointer */ ++#include <../lx2160asi/bootlocptr_nor.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Errata for PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_24.rcw> +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0002-Set-io-pads-as-GPIO.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0002-Set-io-pads-as-GPIO.patch new file mode 100644 index 00000000..b156a018 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0002-Set-io-pads-as-GPIO.patch @@ -0,0 +1,38 @@ +From b184697cff85d8f98e765014309b97444ff1c5b7 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Wed, 30 Oct 2019 11:43:37 +0200 +Subject: [PATCH 2/2] Set io pads as GPIO + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index 6fd65ec..dbc843f 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -9,11 +9,16 @@ HWA_CGA_M1_CLK_SEL=1 + HWA_CGB_M1_CLK_SEL=7 + BOOT_LOC=26 + SYSCLK_FREQ=600 +-IIC2_PMUX=6 ++IIC2_PMUX=1 + IIC3_PMUX=0 + IIC4_PMUX=2 + USB3_CLK_FSEL=39 + SRDS_DIV_PEX_S1=1 + SRDS_DIV_PEX_S2=3 + SRDS_DIV_PEX_S3=1 +- ++SDHC1_DIR_PMUX=1 ++IRQ03_00_PMUX=1 ++IRQ07_04_PMUX=1 ++IRQ11_08_PMUX=1 ++EVT20_PMUX=1 ++EVT43_PMUX=1 +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch new file mode 100644 index 00000000..18d37a65 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch @@ -0,0 +1,42 @@ +From 3b0e8b6e242549c2ed992d7556d7966a77b6da86 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 5 Nov 2019 10:35:32 +0200 +Subject: [PATCH] S2 - enable gen3, xspi increase divisor to 28 + +Serdes group 2 enable PCIe gen 3 +XSPI increase divisor to 28 - this fixes UEFI SPI flash detection. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +- + lx2160acex7/configs/lx2160a_xspiboot.rcwi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index dbc843f..3ea7683 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -14,7 +14,7 @@ IIC3_PMUX=0 + IIC4_PMUX=2 + USB3_CLK_FSEL=39 + SRDS_DIV_PEX_S1=1 +-SRDS_DIV_PEX_S2=3 ++SRDS_DIV_PEX_S2=1 + SRDS_DIV_PEX_S3=1 + SDHC1_DIR_PMUX=1 + IRQ03_00_PMUX=1 +diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +index eecc314..28310c9 100644 +--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi ++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +@@ -14,4 +14,4 @@ + #include <../lx2160asi/common.rcw> + + /* Modify FlexSPI Clock Divisor value */ +-#include <../lx2160asi/flexspi_divisor_24.rcw> ++#include <../lx2160asi/flexspi_divisor_28.rcw> +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0004-refactor-a009531-a008851-and-a011270.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0004-refactor-a009531-a008851-and-a011270.patch new file mode 100644 index 00000000..0bcc5d33 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0004-refactor-a009531-a008851-and-a011270.patch @@ -0,0 +1,181 @@ +From c7c3ed47f1de7c20de348a6ca5fe0d5a18912f4b Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 12:16:13 +0200 +Subject: [PATCH 4/4] refactor a009531, a008851 and a011270 + +1. Add 'load conditional', 'jump condidional' and 'jump' to PBI +instructions. +2. Use SVR register to execute the PCIe workarounds on the relevant rev +of the device. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160asi/a009531_a008851.rcw | 96 +++++++++++++++++++++++++++++++++++ + lx2160asi/a011270.rcw | 6 +++ + rcw.py | 28 ++++++++++ + 3 files changed, 130 insertions(+) + create mode 100644 lx2160asi/a009531_a008851.rcw + +diff --git a/lx2160asi/a009531_a008851.rcw b/lx2160asi/a009531_a008851.rcw +new file mode 100644 +index 0000000..0eb7051 +--- /dev/null ++++ b/lx2160asi/a009531_a008851.rcw +@@ -0,0 +1,96 @@ ++/* ++ * Work-around for erratum A-009531 ++ * ++ * Description: ++ * As defined in section 2.2.6.4, Relaxed Ordering and ID-Based Ordering (IDO) ++ * Attributes of the PCI Express Base Specification Rev 3.1, “A Completer ++ * is permitted to set IDO only if the IDO Completion Enable bit in the Device ++ * Control 2 Register is set. It is not required to copy the value of IDO from ++ * the Request into the Completion(s) for that Request". ++ * ++ * However, the PCI Express controller as the completer sets the IDO bit in the ++ * completion packet header, in response to non-posted requests (memory read) with ++ * IDO bit set in the packet header, even if the IDO Completion Enable bit in the ++ * Device Control 2 Register is not set. ++ * ++ * Impact: ++ * The PCI Express controller as the completer sends completion packets with IDO ++ * bit set in packet header even when the IDO Completion Enable bit is cleared in ++ * the controller’s Device Control 2 Register. ++ * Applicable for SNP PCIe controller ++ */ ++ ++/* ++ * Work-around for erratum A-008851 ++ * ++ * Invalid transmitter/receiver preset values are used in Gen3 equalization ++ * phases during link training for RC mode ++ * This errata is valid only for PCI gen3. ++ * Workaround: ++ * write 0x00000001 to MISC_CONTROL_1_OFF ++ * write 0x4747 to Lane Equalization Control register for each lane ++ * Applicable for SNP PCIe controller ++ */ ++ ++.pbi ++/* Load condition SVR register mask major ID */ ++loadc 0x01e000a4,0x000000f0 ++ ++/* If it is rev 2, skip the following jump command */ ++jumpc 0x00000014,0x00000020 ++ ++/* Jump all the below instructions */ ++jump 0x190 /* All instruction below including the jump are 0x190 bytes */ ++ ++loadc 0x01ea1080,0x70000000 ++jumpc 0x00000034,0x00000000 ++write 0x03400098,0x00000000 ++write 0x034008bc,0x00000001 ++write 0x03400154,0x47474747 ++write 0x03400158,0x47474747 ++write 0x034008bc,0x00000000 ++ ++loadc 0x01ea1080,0x00700000 ++jumpc 0x00000034,0x00000000 ++write 0x03500098,0x00000000 ++write 0x035008bc,0x00000001 ++write 0x03500154,0x47474747 ++write 0x03500158,0x47474747 ++write 0x035008bc,0x00000000 ++ ++loadc 0x01eb1080,0x70000000 ++jumpc 0x00000044,0x00000000 ++write 0x03600098,0x00000000 ++write 0x036008bc,0x00000001 ++write 0x03600164,0x47474747 ++write 0x03600168,0x47474747 ++write 0x0360016c,0x47474747 ++write 0x03600170,0x47474747 ++write 0x036008bc,0x00000000 ++ ++loadc 0x01eb1080,0x00700000 ++jumpc 0x00000034,0x00000000 ++write 0x03700098,0x00000000 ++write 0x037008bc,0x00000001 ++write 0x03700154,0x47474747 ++write 0x03700158,0x47474747 ++write 0x037008bc,0x00000000 ++ ++loadc 0x01ec1080,0x70000000 ++jumpc 0x00000044,0x00000000 ++write 0x03800098,0x00000000 ++write 0x038008bc,0x00000001 ++write 0x03800164,0x47474747 ++write 0x03800168,0x47474747 ++write 0x0380016c,0x47474747 ++write 0x03800170,0x47474747 ++write 0x038008bc,0x00000000 ++ ++loadc 0x01ec1080,0x00700000 ++jumpc 0x00000034,0x00000000 ++write 0x03900098,0x00000000 ++write 0x039008bc,0x00000001 ++write 0x03900154,0x47474747 ++write 0x03900158,0x47474747 ++write 0x039008bc,0x00000000 ++.end +diff --git a/lx2160asi/a011270.rcw b/lx2160asi/a011270.rcw +index 0dc774d..5bd5558 100644 +--- a/lx2160asi/a011270.rcw ++++ b/lx2160asi/a011270.rcw +@@ -4,6 +4,12 @@ + */ + + .pbi ++/* Load condition SVR register mask major ID */ ++loadc 0x01e000a4,0x000000f0 ++/* If it is rev 1, skip the following jump command */ ++jumpc 0x00000014,0x00000010 ++/* Skip the following instructions by jumping to the end */ ++jump 0x38 + write 0x03400688,0x00000001 + write 0x03500688,0x00000001 + write 0x03600688,0x00000001 +diff --git a/rcw.py b/rcw.py +index 863f755..c2d06f6 100755 +--- a/rcw.py ++++ b/rcw.py +@@ -328,6 +328,34 @@ def build_pbi(lines): + v2 = struct.pack(endianess + 'L', p2) + subsection += v1 + subsection += v2 ++ elif op == 'loadc': ++ if p1 == None or p2 == None: ++ print('Error: "loadc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80140000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jumpc': ++ if p1 == None or p2 == None: ++ print('Error: "jumpc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80850000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jump': ++ if p1 == None: ++ print('Error: "jump" instruction requires a parameter') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80840000) ++ v2 = struct.pack(endianess + 'L', p1) ++ subsection += v1 ++ subsection += v2 + elif op == 'awrite': + if p1 == None or p2 == None: + print('Error: "awrite" instruction requires two parameters') +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch new file mode 100644 index 00000000..68091513 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch @@ -0,0 +1,32 @@ +From 2ebdb6a46e6db66cc0b09c51260a90ea8abc4713 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 12:35:04 +0200 +Subject: [PATCH 6/8] lx2160a: add SVR check for a050234 to apply only on rev1 + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160asi/a050234.rcw | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/lx2160asi/a050234.rcw b/lx2160asi/a050234.rcw +index 72a40e4..2130709 100644 +--- a/lx2160asi/a050234.rcw ++++ b/lx2160asi/a050234.rcw +@@ -4,6 +4,12 @@ + */ + + .pbi ++/* Load condition SVR register mask major ID */ ++loadc 0x01e000a4,0x000000f0 ++/* If it is rev 1, skip the following jump command */ ++jumpc 0x00000014,0x00000010 ++/* Skip the following instructions by jumping to the end */ ++jump 0xc8 + write 0x1ea1200,0x20081004 + write 0x1ea1240,0x20081004 + write 0x1ea1280,0x20081004 +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch new file mode 100644 index 00000000..9074b5cc --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch @@ -0,0 +1,95 @@ +From 6d634d64528e5ba510c369a2ae19c337ae7d692e Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 12:36:20 +0200 +Subject: [PATCH 7/8] lx2160acex7 - pcie workarounds and fan full speed + +1. Moves calling the workarounds to the _defaults.rcwi +2. Toggle fan-full-speed GPIO. The fan controller starts throttling when +a driver exists (i.e. kernel); in order to avoid overheating until then +enable full speed. +3. Run a050234.rcw on rev1 - fixes some issues observed when using Mellanox +ConnectX-5 NICs +4. Run a009531 and a00885 on rev2. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 21 +++++++++++++++++---- + lx2160acex7/configs/lx2160a_sdboot.rcwi | 6 ------ + lx2160acex7/configs/lx2160a_xspiboot.rcwi | 6 ------ + 3 files changed, 17 insertions(+), 16 deletions(-) + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index 3ea7683..7af1f5b 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -1,10 +1,6 @@ + #include <../lx2160asi/lx2160a.rcwi> + MEM_PLL_CFG=3 + MEM2_PLL_CFG=3 +-C5_PLL_SEL=0 +-C6_PLL_SEL=0 +-C7_PLL_SEL=0 +-C8_PLL_SEL=0 + HWA_CGA_M1_CLK_SEL=1 + HWA_CGB_M1_CLK_SEL=7 + BOOT_LOC=26 +@@ -22,3 +18,20 @@ IRQ07_04_PMUX=1 + IRQ11_08_PMUX=1 + EVT20_PMUX=1 + EVT43_PMUX=1 ++ ++/* Drive the fan full speed pin */ ++.pbi ++write 0x2320000,0x20000000 ++.end ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Errata for rev 1 PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++ ++/* Errata a050234 - fix elastic buffer threshold in rev 1 */ ++#include <../lx2160asi/a050234.rcw> ++ ++/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/ ++#include <../lx2160asi/a009531_a008851.rcw> +diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi +index d537ea5..9086ffc 100644 +--- a/lx2160acex7/configs/lx2160a_sdboot.rcwi ++++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi +@@ -9,12 +9,6 @@ blockcopy 0x08,0x00100000,0x1800a000,0x00020000 + /* Boot Location Pointer */ + #include <../lx2160asi/bootlocptr_sd.rcw> + +-/* Errata for SATA controller */ +-#include <../lx2160asi/a010554.rcw> +- +-/* Errata for PCIe controller */ +-#include <../lx2160asi/a011270.rcw> +- + /* common PBI commands */ + #include <../lx2160asi/common.rcw> + +diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +index 28310c9..fa092c9 100644 +--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi ++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +@@ -4,12 +4,6 @@ + /* Boot Location Pointer */ + #include <../lx2160asi/bootlocptr_nor.rcw> + +-/* Errata for SATA controller */ +-#include <../lx2160asi/a010554.rcw> +- +-/* Errata for PCIe controller */ +-#include <../lx2160asi/a011270.rcw> +- + /* common PBI commands */ + #include <../lx2160asi/common.rcw> + +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0008-lx2160a-add-generic-bootloc-section.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0008-lx2160a-add-generic-bootloc-section.patch new file mode 100644 index 00000000..820f7b21 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0008-lx2160a-add-generic-bootloc-section.patch @@ -0,0 +1,113 @@ +From f7f0ad5e568862f7dc70fbd0f790845ee576734d Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 24 Mar 2020 03:42:14 +0200 +Subject: [PATCH 8/8] lx2160a: add generic bootloc section + +The generic bootloc section does conditional blockcopy from SD/eMMC and +SPI with some predefined addresses. +Later on if ATF is used; those addresses are modified with ATF's +create_pbl.c + +With this method a single boot image is unified for all the 3 different +boot methods. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 12 +++++ + lx2160asi/bootlocptr.rcw | 62 +++++++++++++++++++++++ + 2 files changed, 74 insertions(+) + create mode 100644 lx2160asi/bootlocptr.rcw + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index 7af1f5b..7997d49 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -35,3 +35,15 @@ write 0x2320000,0x20000000 + + /* LX2 rev 2 PCIe Errata A-009531 and A-008851*/ + #include <../lx2160asi/a009531_a008851.rcw> ++ ++/* Unified boot location copy */ ++#include <../lx2160asi/bootlocptr.rcw> ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160asi/bootlocptr.rcw b/lx2160asi/bootlocptr.rcw +new file mode 100644 +index 0000000..645182f +--- /dev/null ++++ b/lx2160asi/bootlocptr.rcw +@@ -0,0 +1,62 @@ ++/* ++ * Generic code for auto booting. ++ * For each section blockcopy followed by write to bootlocl then bootloch must ++ * be followed in each section since when using ATF with create_pbl script in ++ * auto mode; it counts on the sequence of to be in that order. ++ */ ++ ++/* Boot from SD - copy SPL Uboot to Ocram */ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0x8 << 23 then skip the following jump command */ ++jumpc 0x00000014,0x04000000 ++ ++/* Jump all the below instructions */ ++jump 0x28 /* All instruction below including the jump are 40 bytes */ ++ ++/* blockcopy must be followed by two writes to bootlocl and bootloch */ ++blockcopy 0x08,0x00100000,0x1800a000,0x00020000 ++write 0x01e00400,0x1800a000 ++write 0x01e00404,0x00000000 ++.end ++ ++/* Boot from eMMC - copy SPL Uboot to Ocram */ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0x9 << 23 then skip the following jump command */ ++jumpc 0x00000014,0x04800000 ++ ++/* Jump all the below instructions */ ++jump 0x28 /* All instruction below including the jump are 40 bytes */ ++ ++/* blockcopy must be followed by two writes to bootlocl and bootloch */ ++blockcopy 0x09,0x00100000,0x1800a000,0x00020000 ++write 0x01e00400,0x1800a000 ++write 0x01e00404,0x00000000 ++.end ++ ++/* XSPI boot Location Pointer */ ++/* ++ * Set the boot location pointer to the NOR flash boot area. ++ */ ++ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0xf << 23 then skip the following jump command */ ++jumpc 0x00000014,0x07800000 ++ ++/* Jump all the below instructions */ ++jump 0x28 /* All instruction below including the jump are 0x190 bytes */ ++ ++/* blockcopy must be followed by two writes to bootlocl and bootloch */ ++blockcopy 0x0f,0x00100000,0x1800a000,0x00020000 ++write 0x01e00400,0x20100000 ++write 0x01e00404,0x00000000 ++.end ++ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0009-lx2160acex7-remove-all-predefined-RCW-files.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0009-lx2160acex7-remove-all-predefined-RCW-files.patch new file mode 100644 index 00000000..20d77e6f --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0009-lx2160acex7-remove-all-predefined-RCW-files.patch @@ -0,0 +1,301 @@ +From 151f650f383fc5ddd9c405cf96bc189c2eaf13bd Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 24 Mar 2020 03:51:28 +0200 +Subject: [PATCH 9/9] lx2160acex7: remove all predefined RCW files + +Remove all predefined RCW files and use on-the-fly created RCW from +external script. +For instance when using lx2160a_build repo; the runme.sh file creates +lx2160acex7/RCW/template.rcw file the gets compiled. +The creation is done using a simple bash script - + +cd $ROOTDIR/build/rcw/lx2160acex7 +mkdir -p RCW +echo "#include <configs/lx2160a_defaults.rcwi>" > RCW/template.rcw +echo "#include <configs/lx2160a_${SPEED}.rcwi>" >> RCW/template.rcw +echo "#include <configs/lx2160a_${SERDES}.rcwi>" >> RCW/template.rcw +make clean +make -j${PARALLEL} + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig | 61 ------------------- + .../rcw_1900_600_2600_17_4_2.rcw | 4 -- + .../rcw_1900_600_2600_17_4_2_sd.rcw | 4 -- + .../rcw_2000_700_2400_13_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2400_20_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2400_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2600_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2900_17_4_2_sd.rcw | 4 -- + .../rcw_2000_700_2900_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_17_4_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_20_5_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_8_5_0_sd.rcw | 4 -- + .../rcw_2000_700_3200_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_8_5_2_xspi.rcw | 4 -- + .../rcw_2400_700_3200_8_5_2_sd.rcw | 4 -- + .../rcw_2500_700_3200_8_5_2_sd.rcw | 4 -- + .../rcw_2600_700_3200_8_5_2_sd.rcw | 4 -- + .../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw | 4 -- + 18 files changed, 129 deletions(-) + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw + +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig +deleted file mode 100644 +index cdb6446..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * SerDes Protocol 1 - 19 +- * SerDes Protocol 2 - 5 +- * SerDes Protocol 3 - 2 +- * +- * Frequencies: +- * Core -- 1900 MHz +- * Platform -- 600 MHz +- * DDR -- 2600 MT/s +- */ +- +-#include <../lx2160asi/lx2160a.rcwi> +- +-SYS_PLL_RAT=12 +-MEM_PLL_CFG=3 +-MEM_PLL_RAT=26 +-MEM2_PLL_CFG=3 +-MEM2_PLL_RAT=26 +-CGA_PLL1_RAT=19 +-CGA_PLL2_RAT=19 +-CGB_PLL1_RAT=19 +-CGB_PLL2_RAT=9 +-C5_PLL_SEL=0 +-C6_PLL_SEL=0 +-C7_PLL_SEL=0 +-C8_PLL_SEL=0 +-HWA_CGA_M1_CLK_SEL=1 +-HWA_CGB_M1_CLK_SEL=7 +-BOOT_LOC=26 +-SYSCLK_FREQ=600 +-IIC2_PMUX=6 +-IIC3_PMUX=2 +-IIC4_PMUX=2 +-USB3_CLK_FSEL=39 +-SRDS_PRTCL_S1=19 +-SRDS_PRTCL_S2=5 +-SRDS_PRTCL_S3=2 +-SRDS_PLL_REF_CLK_SEL_S1=2 +-SRDS_DIV_PEX_S1=1 +-SRDS_DIV_PEX_S2=3 +-SRDS_DIV_PEX_S3=1 +- +-/* Errata to write on scratch reg for validation */ +-#include <../lx2160asi/scratchrw1.rcw> +- +-/* Copy SPL Uboot to Ocram */ +-.pbi +-blockcopy 0x08,0x00100000,0x1800a000,0x00020000 +-.end +- +-/* Boot Location Pointer */ +-#include <../lx2160asi/bootlocptr_sd.rcw> +- +-/* Errata for SATA controller */ +-#include <../lx2160asi/a010554.rcw> +- +-/* Modify FlexSPI Clock Divisor value */ +-#include <../lx2160asi/flexspi_divisor_24.rcw> +- +-/* common PBI commands */ +-#include <../lx2160asi/common.rcw> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw +deleted file mode 100644 +index 13ab0b9..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_1900_600_2600.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw +deleted file mode 100644 +index 14fae8c..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_1900_600_2600.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw +deleted file mode 100644 +index 2dae5a2..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2400.rcwi> +-#include <configs/lx2160a_13_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw +deleted file mode 100644 +index 5335072..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2400.rcwi> +-#include <configs/lx2160a_20_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw +deleted file mode 100644 +index e2a5bd3..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2400.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw +deleted file mode 100644 +index a330bfe..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2600.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw +deleted file mode 100644 +index 8535dbd..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2900.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw +deleted file mode 100644 +index 698be01..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2900.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw +deleted file mode 100644 +index 780d8c3..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw +deleted file mode 100644 +index eb9d240..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_20_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw +deleted file mode 100644 +index ceb53a3..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_8_5_0.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index a220e98..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw +deleted file mode 100644 +index 1eabd7d..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index 2ac59b1..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2400_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index e7c08df..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2500_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index 1e7a8f7..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2600_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw +deleted file mode 100644 +index 86f12f8..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_test.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw_git.bbappend b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw_git.bbappend new file mode 100644 index 00000000..4384c042 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw_git.bbappend @@ -0,0 +1,29 @@ +FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:" + +SRC_URI_append_lx2160acex7 = "\ + file://0001-lx2160acex7-misc-RCW-files.patch \ + file://0002-Set-io-pads-as-GPIO.patch \ + file://0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch \ + file://0004-refactor-a009531-a008851-and-a011270.patch \ + file://0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch \ + file://0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch \ + file://0008-lx2160a-add-generic-bootloc-section.patch \ + file://0009-lx2160acex7-remove-all-predefined-RCW-files.patch \ +" + +do_configure_prepend_lx2160acex7 () { + for BT in ${BOARD_TARGETS} + do + mkdir -p ${S}/${BOARD_TARGETS}/${SERDES} + cat <<EOF >${S}/${BOARD_TARGETS}/README +The RCW directories for lx2160acex7 are created based on existing SERDES +configuration. Currently created automatically - later maybe by building +cross product of serdes & ddr speeds in a final commit. +EOF + cat <<EOF >${S}/${BOARD_TARGETS}/${SERDES}/${SPEED}.rcw +#include <configs/lx2160a_defaults.rcwi> +#include <configs/lx2160a_${SPEED}.rcwi> +#include <configs/lx2160a_${SERDES}.rcwi> +EOF + done +} diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-common_2018.07.inc b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-common_2018.07.inc index 59b17cce..d5adb0e5 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-common_2018.07.inc +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-common_2018.07.inc @@ -4,10 +4,10 @@ LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" PV = "v2018.07+git${SRCPV}" -SRCREV = "ca185fc7406207da613c728935f534a4054674f1" +SRCREV = "17fe0ef3aff3abc3908c854bfab1c283ed84d9c0" SRCBRANCH = "boundary-v2018.07" SRC_URI = "git://github.com/boundarydevices/u-boot-imx6.git;branch=${SRCBRANCH}" S = "${WORKDIR}/git" - +B = "${WORKDIR}/build" PACKAGE_ARCH = "${MACHINE_ARCH}" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils/aarch64/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils/aarch64/fw_env.config deleted file mode 100644 index eccfb0f4..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils/aarch64/fw_env.config +++ /dev/null @@ -1 +0,0 @@ -/dev/mmcblk0boot0 0x1fe000 0x2000 0x1000 diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils_2018.07.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils_2018.07.bb deleted file mode 100644 index 6b8fb867..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils_2018.07.bb +++ /dev/null @@ -1,46 +0,0 @@ -require u-boot-boundary-common_${PV}.inc - -SUMMARY = "U-Boot bootloader fw_printenv/setenv utilities" -DEPENDS += "mtd-utils bison-native" - -FILESEXTRAPATHS_prepend_mx6 := "${THISDIR}/${PN}/arm:" -FILESEXTRAPATHS_prepend_mx7 := "${THISDIR}/${PN}/arm:" -FILESEXTRAPATHS_prepend_mx8 := "${THISDIR}/${PN}/aarch64:" - -SRC_URI += " \ - file://fw_env.config \ -" - -INSANE_SKIP_${PN} = "already-stripped" -EXTRA_OEMAKE_class-target = 'CROSS_COMPILE=${TARGET_PREFIX} CC="${CC} ${CFLAGS} ${LDFLAGS}" HOSTCC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}" V=1' -EXTRA_OEMAKE_class-cross = 'ARCH=${TARGET_ARCH} CC="${CC} ${CFLAGS} ${LDFLAGS}" V=1' - -inherit uboot-config - -do_compile () { - oe_runmake ${UBOOT_MACHINE} - oe_runmake envtools -} - -do_install () { - install -Dm 0755 ${S}/tools/env/fw_printenv ${D}${base_sbindir}/fw_printenv - install -Dm 0755 ${S}/tools/env/fw_printenv ${D}${base_sbindir}/fw_setenv - install -Dm 0644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config -} - -do_install_class-cross () { - install -d ${D}${bindir_cross} - install -m 755 ${S}/tools/env/fw_printenv ${D}${bindir_cross}/fw_printenv - install -m 755 ${S}/tools/env/fw_printenv ${D}${bindir_cross}/fw_setenv -} - -SYSROOT_PREPROCESS_FUNCS_class-cross = "uboot_fw_utils_cross" -uboot_fw_utils_cross() { - sysroot_stage_dir ${D}${bindir_cross} ${SYSROOT_DESTDIR}${bindir_cross} -} - -RPROVIDES_${PN} += "u-boot-fw-utils" - -BBCLASSEXTEND = "cross" - -COMPATIBLE_MACHINE = "(imx)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary/aarch64/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary/aarch64/fw_env.config new file mode 100644 index 00000000..b69cec9e --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary/aarch64/fw_env.config @@ -0,0 +1 @@ +/dev/mmcblk0boot0 0x3fe000 0x2000 0x1000 diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils/arm/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary/arm/fw_env.config index 571e829c..571e829c 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary-fw-utils/arm/fw_env.config +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary/arm/fw_env.config diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary_2018.07.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary_2018.07.bb index d9417f54..7463eeea 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary_2018.07.bb +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-boundary_2018.07.bb @@ -1,17 +1,23 @@ require recipes-bsp/u-boot/u-boot.inc require recipes-bsp/u-boot/u-boot-boundary-common_${PV}.inc +FILESEXTRAPATHS_prepend_mx6 := "${THISDIR}/${PN}/arm:" +FILESEXTRAPATHS_prepend_mx7 := "${THISDIR}/${PN}/arm:" +FILESEXTRAPATHS_prepend_mx8 := "${THISDIR}/${PN}/aarch64:" + DEPENDS += "bison-native" +SRC_URI += "file://fw_env.config" + PROVIDES += "u-boot" BOOT_TOOLS = "imx-boot-tools" -do_deploy_append_mx8mq () { +do_deploy_append_mx8 () { install -d ${DEPLOYDIR}/${BOOT_TOOLS} install -m 0777 ${B}/${config}/arch/arm/dts/${UBOOT_DTB_NAME} ${DEPLOYDIR}/${BOOT_TOOLS} install -m 0777 ${B}/${config}/tools/mkimage ${DEPLOYDIR}/${BOOT_TOOLS}/mkimage_uboot - install -m 0777 ${B}/${config}/u-boot-nodtb.bin ${DEPLOYDIR}/${BOOT_TOOLS} + install -m 0777 ${B}/${config}/u-boot-nodtb.bin ${DEPLOYDIR}/${BOOT_TOOLS}/u-boot-nodtb.bin-${MACHINE}-${UBOOT_CONFIG} } -COMPATIBLE_MACHINE = "(nitrogen6x-lite|nitrogen6x|nitrogen6sx|nitrogen7|nitrogen8m)" +COMPATIBLE_MACHINE = "(nitrogen6x-lite|nitrogen6x|nitrogen6sx|nitrogen7|nitrogen8m|nitrogen8mm|nitrogen8mn)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-compulab_2014.10.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-compulab_2014.10.bb deleted file mode 100644 index 02651e09..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-compulab_2014.10.bb +++ /dev/null @@ -1,17 +0,0 @@ -require recipes-bsp/u-boot/u-boot.inc - -DESCRIPTION = "u-boot which includes support for CompuLab boards." -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://configs/cm_fx6_defconfig;md5=549452418e9e099e5fe19ef1ac65e892" - -PROVIDES += "u-boot" - -SRCBRANCH = "utilite/master" -SRCREV = "6803a75f3d40bee3b53f56e7b49c70465819b7ca" -SRC_URI = "git://github.com/utilite-computer/u-boot.git;branch=${SRCBRANCH}" -SRC_URI[md5sum] = "fd8234c5b3a460430689848c1f16acef" - -S = "${WORKDIR}/git" - -PACKAGE_ARCH = "${MACHINE_ARCH}" -COMPATIBLE_MACHINE = "cm-fx6" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-digi/ccimx6ul/bootscript.txt b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-digi/ccimx6ul/bootscript.txt deleted file mode 100644 index 06b42bed..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-digi/ccimx6ul/bootscript.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# U-Boot bootscript for NAND images created by Yocto. -# - -setenv fdt_file imx6ul-ccimx6ulsbcexpress.dtb -setenv zimage zImage-ccimx6ulsbcexpress.bin -dboot linux nand ${mtdbootpart} diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-digi_2017.03.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-digi_2017.03.bb deleted file mode 100644 index aa775727..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-digi_2017.03.bb +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright (C) 2018 Digi International -# Released under the MIT license (see COPYING.MIT for the terms) - -DESCRIPTION = "Bootloader for Digi platforms" -SECTION = "bootloaders" -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" - -require recipes-bsp/u-boot/u-boot.inc - -DEPENDS = "u-boot-mkimage-native" - -PROVIDES += "u-boot" - -SRCBRANCH = "v2017.03/maint" -SRCREV = "8d60f536d2063ac6a0676bdf34c4c8c8807371c5" - -SRC_URI = "\ - git://github.com/digi-embedded/u-boot.git;protocol=git;nobranch=1 \ - file://bootscript.txt \ -" - -LOCALVERSION ?= "-${SRCBRANCH}" - -S = "${WORKDIR}/git" - -inherit dtc-145 fsl-u-boot-localversion - -UBOOT_ENV = "boot" -UBOOT_ENV_SUFFIX = "scr" - -do_compile_append () { - uboot-mkimage -A arm -O linux -T script -C none -a 0 -e 0 \ - -n "boot script" -d ${WORKDIR}/bootscript.txt \ - ${WORKDIR}/${UBOOT_ENV_BINARY} -} - -PACKAGE_ARCH = "${MACHINE_ARCH}" - -COMPATIBLE_MACHINE = "(ccimx6ul)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-karo_git.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-karo_git.bb deleted file mode 100644 index 2e1f7bb1..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-karo_git.bb +++ /dev/null @@ -1,19 +0,0 @@ -require recipes-bsp/u-boot/u-boot.inc - -DESCRIPTION = "u-boot for Ka-Ro electronics TX Computer-On-Modules." -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://Licenses/README;md5=0507cd7da8e7ad6d6701926ec9b84c95" - -PROVIDES = "u-boot" - -PV = "v2015.10-rc2+git${SRCPV}" - -SRCREV = "047997571bf2c5bd43058c8e9da8052e09d9111f" -SRCBRANCH = "karo-tx6" -SRC_URI = "git://git.karo-electronics.de/karo-tx-uboot.git;branch=${SRCBRANCH}" - -S = "${WORKDIR}/git" - -PACKAGE_ARCH = "${MACHINE_ARCH}" - -COMPATIBLE_MACHINE = "(tx6[qsu]-.*)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-kontron/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-kontron/fw_env.config new file mode 100644 index 00000000..a296d5d3 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-kontron/fw_env.config @@ -0,0 +1 @@ +/dev/mmcblk0 0xf0000 0x10000 diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-kontron_2020.01.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-kontron_2020.01.bb new file mode 100644 index 00000000..ce33f8ef --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-kontron_2020.01.bb @@ -0,0 +1,37 @@ +# Copyright (C) 2012-2019 O.S. Systems Software LTDA. +# Released under the MIT license (see COPYING.MIT for the terms) + +inherit fsl-u-boot-localversion + +require recipes-bsp/u-boot/u-boot.inc + +SUMMARY = "U-Boot for Kontron based boards" +DEPENDS += "bison-native bc-native dtc-native lzop-native" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" + +SRC_URI = "git://git.kontron-electronics.de/linux/u-boot.git;protocol=https;branch=${SRCBRANCH} \ + file://fw_env.config \ +" +SRCREV = "3d58441adf3e633279db6c96acb33a7aef4fd6f9" +SRCBRANCH = "v2020.01-ktn" +LOCALVERSION = "-ktn" + +PROVIDES += "u-boot" + +PV .= "+git${SRCPV}" + +S = "${WORKDIR}/git" +B = "${WORKDIR}/build" + +# FIXME: Allow linking of 'tools' binaries with native libraries +# used for generating the boot logo and other tools used +# during the build process. +EXTRA_OEMAKE += 'HOSTCC="${BUILD_CC} ${BUILD_CPPFLAGS}" \ + HOSTLDFLAGS="${BUILD_LDFLAGS}" \ + HOSTSTRIP=true' + +PACKAGE_ARCH = "${MACHINE_ARCH}" +COMPATIBLE_MACHINE = "(imx6ul-kontron)" + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0001-armv8-add-lx2160acex7-build-inclusion.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0001-armv8-add-lx2160acex7-build-inclusion.patch new file mode 100644 index 00000000..7837bfff --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0001-armv8-add-lx2160acex7-build-inclusion.patch @@ -0,0 +1,75 @@ +From c24c3ec7d9591cf359ac12f656bd59a5440532f4 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 13:26:45 +0300 +Subject: [PATCH 01/17] armv8: add lx2160acex7 build inclusion + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + arch/arm/Kconfig | 13 +++++++++++++ + arch/arm/cpu/armv8/Kconfig | 2 +- + arch/arm/dts/Makefile | 3 ++- + 3 files changed, 16 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 5d33526ae9..8615e1673f 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1189,6 +1189,18 @@ config TARGET_LX2160ARDB + is a high-performance development platform that supports the + QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. + ++config TARGET_LX2160ACEX7 ++ bool "Support lx2160acex7" ++ select ARCH_LX2160A ++ select ARCH_MISC_INIT ++ select ARM64 ++ select ARMV8_MULTIENTRY ++ select BOARD_LATE_INIT ++ help ++ Support for SolidRun LX2160A based com express type 7 module and ++ platform. The lx2160acex7 high-performance platform that supports the ++ QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. ++ + config TARGET_LX2160AQDS + bool "Support lx2160aqds" + select ARCH_LX2160A +@@ -1796,6 +1808,7 @@ source "board/freescale/ls1012aqds/Kconfig" + source "board/freescale/ls1012ardb/Kconfig" + source "board/freescale/ls1012afrdm/Kconfig" + source "board/freescale/lx2160a/Kconfig" ++source "board/solidrun/lx2160a/Kconfig" + source "board/freescale/mx35pdk/Kconfig" + source "board/freescale/s32v234evb/Kconfig" + source "board/grinn/chiliboard/Kconfig" +diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig +index 92a2b58ed4..9df6ebdc1b 100644 +--- a/arch/arm/cpu/armv8/Kconfig ++++ b/arch/arm/cpu/armv8/Kconfig +@@ -109,7 +109,7 @@ config PSCI_RESET + !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ + !TARGET_LS1046AFRWY && \ + !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ +- !TARGET_LX2160AQDS && \ ++ !TARGET_LX2160AQDS && !TARGET_LX2160ACEX7 && \ + !ARCH_UNIPHIER && !TARGET_S32V234EVB + help + Most armv8 systems have PSCI support enabled in EL3, either through +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 8d7d5bee45..6d8d7fa09e 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -348,7 +348,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls1028a-qds-duart.dtb \ + fsl-ls1028a-qds-lpuart.dtb \ + fsl-lx2160a-rdb.dtb \ +- fsl-lx2160a-qds.dtb ++ fsl-lx2160a-qds.dtb \ ++ fsl-lx2160a-cex7.dtb + dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ + fsl-ls1043a-qds-lpuart.dtb \ + fsl-ls1043a-rdb.dtb \ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0002-armv8-lx2160acex-misc-hacks-to-get-the-sources-built.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0002-armv8-lx2160acex-misc-hacks-to-get-the-sources-built.patch new file mode 100644 index 00000000..5b8d07f1 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0002-armv8-lx2160acex-misc-hacks-to-get-the-sources-built.patch @@ -0,0 +1,44 @@ +From a8a182b435e96a22b01d722a8df3061c1a1b7da6 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 13:27:46 +0300 +Subject: [PATCH 02/17] armv8: lx2160acex: misc hacks to get the sources built + +those hacks will be sorted out nicer in the future and this patch will +not be needed anymore + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 - + drivers/mmc/fsl_esdhc.c | 2 +- + 2 files changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +index 42ca990994..efdc31da5d 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig ++++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +@@ -218,7 +218,6 @@ config ARCH_LX2160A + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 +- select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC +diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c +index f8e6ceba06..f4a7698cfd 100644 +--- a/drivers/mmc/fsl_esdhc.c ++++ b/drivers/mmc/fsl_esdhc.c +@@ -1020,7 +1020,7 @@ static int fsl_esdhc_probe(struct udevice *dev) + priv->non_removable = 0; + } + +- priv->wp_enable = 1; ++ priv->wp_enable = 0; + + if (IS_ENABLED(CONFIG_CLK)) { + /* Assigned clock already set clock */ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch new file mode 100644 index 00000000..cb968445 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch @@ -0,0 +1,192 @@ +From caaf386e5511e8b9708abf9ee52b668019a5b094 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 13:29:31 +0300 +Subject: [PATCH 03/17] armv8: lx2160acex7: defconfig and main platform include + +This patch add lx2160acex7 main defconfig and main include file. +Notice that the defconfig doesn't support the secured boot mode where a +follow up patch will cover this. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + configs/lx2160acex7_tfa_defconfig | 73 ++++++++++++++++++++++++++ + include/configs/lx2160acex7.h | 85 +++++++++++++++++++++++++++++++ + 2 files changed, 158 insertions(+) + create mode 100644 configs/lx2160acex7_tfa_defconfig + create mode 100644 include/configs/lx2160acex7.h + +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +new file mode 100644 +index 0000000000..d59de7d054 +--- /dev/null ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -0,0 +1,73 @@ ++CONFIG_ARM=y ++CONFIG_TARGET_LX2160ACEX7=y ++CONFIG_SYS_TEXT_BASE=0x82000000 ++CONFIG_SYS_MALLOC_F_LEN=0x6000 ++CONFIG_EMC2301=y ++CONFIG_TFABOOT=y ++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y ++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y ++CONFIG_AHCI=y ++CONFIG_NR_DRAM_BANKS=3 ++CONFIG_FIT_VERBOSE=y ++CONFIG_OF_BOARD_SETUP=y ++CONFIG_OF_BOARD_FIXUP=y ++CONFIG_OF_STDOUT_VIA_ALIAS=y ++CONFIG_BOOTDELAY=10 ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" ++# CONFIG_USE_BOOTCOMMAND is not set ++CONFIG_CMD_GREPENV=y ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_CACHE=y ++CONFIG_MP=y ++CONFIG_OF_CONTROL=y ++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_DM=y ++CONFIG_SATA_CEVA=y ++CONFIG_FSL_CAAM=y ++CONFIG_DM_MMC=y ++CONFIG_FSL_ESDHC=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_MICRON=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_PHYLIB=y ++CONFIG_NETDEVICES=y ++CONFIG_PHY_GIGE=y ++CONFIG_CMD_NET=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_EXT2=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_DM_PCI_COMPAT=y ++CONFIG_PCIE_LAYERSCAPE_GEN4=y ++CONFIG_PHY_ATHEROS=y ++CONFIG_E1000=y ++CONFIG_DM_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_SERIAL_PROBE_ALL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_NXP_FSPI=y ++# CONFIG_SYS_NXP_FSPI_AHB=y ++CONFIG_USB=y ++CONFIG_DM_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h +new file mode 100644 +index 0000000000..478cd8242f +--- /dev/null ++++ b/include/configs/lx2160acex7.h +@@ -0,0 +1,85 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2019 SolidRun ltd. ++ */ ++ ++#ifndef __LX2_CEX7_H ++#define __LX2_CEX7_H ++ ++#include "lx2160a_common.h" ++ ++/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/ ++/* VID */ ++ ++#define I2C_MUX_CH_VOL_MONITOR 0x2 ++/* Voltage monitor on channel 2*/ ++#define I2C_VOL_MONITOR_ADDR 0x5c ++#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 ++#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 ++#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 ++#define CONFIG_VID_FLS_ENV "lx2160acex7_vdd_mv" ++#define CONFIG_VID ++ ++/* The lowest and highest voltage allowed*/ ++#define VDD_MV_MIN 700 ++#define VDD_MV_MAX 855 ++ ++/* PM Bus commands code for LTC3882*/ ++#define PMBUS_CMD_PAGE 0x0 ++#define PMBUS_CMD_READ_VOUT 0x8B ++#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 ++#define PMBUS_CMD_VOUT_COMMAND 0x21 ++#define PWM_CHANNEL0 0x0 ++ ++#define CONFIG_VOL_MONITOR_LTC3882_SET ++#define CONFIG_VOL_MONITOR_LTC3882_READ ++ ++/* RTC */ ++#define CONFIG_SYS_RTC_BUS_NUM 4 ++ ++/* MAC/PHY configuration */ ++#if defined(CONFIG_FSL_MC_ENET) ++#define CONFIG_MII ++#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" ++ ++#define RGMII_PHY_ADDR1 0x01 ++ ++#endif ++ ++/* EMC2301 */ ++#define I2C_MUX_CH_EMC2301 0x01 ++#define I2C_EMC2301_ADDR 0x2f ++#define I2C_EMC2301_CMD 0x40 ++#define I2C_EMC2301_PWM 0x80 ++ ++/* EEPROM */ ++#undef CONFIG_ID_EEPROM /* Fixme */ ++#define CONFIG_SYS_I2C_EEPROM_NXID ++#define CONFIG_SYS_EEPROM_BUS_NUM 0 ++#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 ++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 ++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 ++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 ++ ++/* Initial environment variables */ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ EXTRA_ENV_SETTINGS \ ++ "lx2160acex7_vdd_mv=800\0" \ ++ "BOARD=lx2160acex7\0" \ ++ "xspi_bootcmd=echo Trying load from flexspi..;" \ ++ "sf probe 0:0 && sf read $load_addr " \ ++ "$kernel_start $kernel_size ; env exists secureboot &&" \ ++ "sf read $kernelheader_addr_r $kernelheader_start " \ ++ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ ++ " bootm $load_addr#$BOARD\0" \ ++ "sd_bootcmd=echo Trying load from sd card..;" \ ++ "mmcinfo; mmc read $load_addr " \ ++ "$kernel_addr_sd $kernel_size_sd ;" \ ++ "env exists secureboot && mmc read $kernelheader_addr_r "\ ++ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ ++ " && esbc_validate ${kernelheader_addr_r};" \ ++ "bootm $load_addr#$BOARD\0" ++ ++#include <asm/fsl_secure_boot.h> ++ ++#endif /* __LX2_CEX7_H */ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0004-armv8-lx2160acex7-common-files-for-platform-support.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0004-armv8-lx2160acex7-common-files-for-platform-support.patch new file mode 100644 index 00000000..cbb2f08c --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0004-armv8-lx2160acex7-common-files-for-platform-support.patch @@ -0,0 +1,1720 @@ +From 568555bb88a6d2880e21f736cfda0b89e89957fa Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 13:31:47 +0300 +Subject: [PATCH 04/17] armv8: lx2160acex7: common files for platform support + +The patch copies and modifies NXP's common platform resources that adds +support to the following - +1. Secureboot +2. Analog devices DC-DC controller +3. EMC2301 PWM fan controller based on NXP's EMC2305 driver + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + board/solidrun/common/Makefile | 24 + + board/solidrun/common/cmd_esbc_validate.c | 85 ++ + board/solidrun/common/emc2301.c | 31 + + board/solidrun/common/emc2301.h | 17 + + board/solidrun/common/fsl_chain_of_trust.c | 164 ++++ + board/solidrun/common/fsl_validate.c | 962 +++++++++++++++++++++ + board/solidrun/common/vid.c | 330 +++++++ + board/solidrun/common/vid.h | 23 + + 8 files changed, 1636 insertions(+) + create mode 100644 board/solidrun/common/Makefile + create mode 100644 board/solidrun/common/cmd_esbc_validate.c + create mode 100644 board/solidrun/common/emc2301.c + create mode 100644 board/solidrun/common/emc2301.h + create mode 100644 board/solidrun/common/fsl_chain_of_trust.c + create mode 100644 board/solidrun/common/fsl_validate.c + create mode 100644 board/solidrun/common/vid.c + create mode 100644 board/solidrun/common/vid.h + +diff --git a/board/solidrun/common/Makefile b/board/solidrun/common/Makefile +new file mode 100644 +index 0000000000..454a18e2f9 +--- /dev/null ++++ b/board/solidrun/common/Makefile +@@ -0,0 +1,24 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ ++MINIMAL= ++ ++ifdef CONFIG_SPL_BUILD ++ifdef CONFIG_SPL_INIT_MINIMAL ++MINIMAL=y ++endif ++endif ++ ++ifdef MINIMAL ++# necessary to create built-in.o ++obj- := __dummy__.o ++else ++obj-$(CONFIG_VID) += vid.o ++obj-$(CONFIG_EMC2301) += emc2301.o ++ifdef CONFIG_SECURE_BOOT ++obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o ++endif ++obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o ++endif +diff --git a/board/solidrun/common/cmd_esbc_validate.c b/board/solidrun/common/cmd_esbc_validate.c +new file mode 100644 +index 0000000000..b06235f291 +--- /dev/null ++++ b/board/solidrun/common/cmd_esbc_validate.c +@@ -0,0 +1,85 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015 Freescale Semiconductor, Inc. ++ */ ++ ++#include <common.h> ++#include <command.h> ++#include <fsl_validate.h> ++ ++int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, ++ char * const argv[]) ++{ ++ if (fsl_check_boot_mode_secure() == 0) { ++ printf("Boot Mode is Non-Secure. Not entering spin loop.\n"); ++ return 0; ++ } ++ ++ printf("Core is entering spin loop.\n"); ++loop: ++ goto loop; ++ ++ return 0; ++} ++ ++#ifndef CONFIG_SPL_BUILD ++static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, ++ char * const argv[]) ++{ ++ char *hash_str = NULL; ++ uintptr_t haddr; ++ int ret; ++ uintptr_t img_addr = 0; ++ char buf[20]; ++ ++ if (argc < 2) ++ return cmd_usage(cmdtp); ++ else if (argc > 2) ++ /* Second arg - Optional - Hash Str*/ ++ hash_str = argv[2]; ++ ++ /* First argument - header address -32/64bit */ ++ haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16); ++ ++ /* With esbc_validate command, Image address must be ++ * part of header. So, the function is called ++ * by passing this argument as 0. ++ */ ++ ret = fsl_secboot_validate(haddr, hash_str, &img_addr); ++ ++ /* Need to set "img_addr" even if validation failure. ++ * Required when SB_EN in RCW set and non-fatal error ++ * to continue U-Boot ++ */ ++ sprintf(buf, "%lx", img_addr); ++ env_set("img_addr", buf); ++ ++ if (ret) ++ return 1; ++ ++ printf("esbc_validate command successful\n"); ++ return 0; ++} ++ ++/***************************************************/ ++static char esbc_validate_help_text[] = ++ "esbc_validate hdr_addr <hash_val> - Validates signature using\n" ++ " RSA verification\n" ++ " $hdr_addr Address of header of the image\n" ++ " to be validated.\n" ++ " $hash_val -Optional\n" ++ " It provides Hash of public/srk key to be\n" ++ " used to verify signature.\n"; ++ ++U_BOOT_CMD( ++ esbc_validate, 3, 0, do_esbc_validate, ++ "Validates signature on a given image using RSA verification", ++ esbc_validate_help_text ++); ++ ++U_BOOT_CMD( ++ esbc_halt, 1, 0, do_esbc_halt, ++ "Put the core in spin loop (Secure Boot Only)", ++ "" ++); ++#endif +diff --git a/board/solidrun/common/emc2301.c b/board/solidrun/common/emc2301.c +new file mode 100644 +index 0000000000..a4780dbfcc +--- /dev/null ++++ b/board/solidrun/common/emc2301.c +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2019 SolidRun ltd. Based on code from NXP LX2160A RDB ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <command.h> ++#include <i2c.h> ++#include <asm/io.h> ++ ++#include "emc2301.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++void set_fan_speed(u8 data) ++{ ++ if (i2c_write(I2C_EMC2301_ADDR, I2C_EMC2301_FAN, 1, &data, 1) != 0) { ++ puts("Error: failed to change fan speed\n"); ++ } ++} ++ ++void emc2301_init(void) ++{ ++ u8 data; ++ ++ data = I2C_EMC2301_CMD; ++ if (i2c_write(I2C_EMC2301_ADDR, I2C_EMC2301_CONF, 1, &data, 1) != 0) ++ puts("Error: failed to configure EMC2301\n"); ++} +diff --git a/board/solidrun/common/emc2301.h b/board/solidrun/common/emc2301.h +new file mode 100644 +index 0000000000..a5ceb73b7c +--- /dev/null ++++ b/board/solidrun/common/emc2301.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2019 SolidRun ltd. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __EMC2301_H_ ++#define __EMC2301_H_ ++ ++#define I2C_EMC2301_CONF 0x20 ++#define I2C_EMC2301_FAN 0x30 ++ ++void emc2301_init(void); ++void set_fan_speed(u8 data); ++ ++#endif /* __EMC2305_H_ */ +diff --git a/board/solidrun/common/fsl_chain_of_trust.c b/board/solidrun/common/fsl_chain_of_trust.c +new file mode 100644 +index 0000000000..dddfd26a13 +--- /dev/null ++++ b/board/solidrun/common/fsl_chain_of_trust.c +@@ -0,0 +1,164 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015 Freescale Semiconductor, Inc. ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <fsl_validate.h> ++#include <fsl_secboot_err.h> ++#include <fsl_sfp.h> ++#include <dm/root.h> ++ ++#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) ++#include <spl.h> ++#endif ++ ++#ifdef CONFIG_ADDR_MAP ++#include <asm/mmu.h> ++#endif ++ ++#ifdef CONFIG_FSL_CORENET ++#include <asm/fsl_pamu.h> ++#endif ++ ++#ifdef CONFIG_ARCH_LS1021A ++#include <asm/arch/immap_ls102xa.h> ++#endif ++ ++#if defined(CONFIG_MPC85xx) ++#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR ++#else ++#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR ++#endif ++ ++#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE ++#define gur_in32(a) in_le32(a) ++#else ++#define gur_in32(a) in_be32(a) ++#endif ++ ++/* Check the Boot Mode. If Secure, return 1 else return 0 */ ++int fsl_check_boot_mode_secure(void) ++{ ++ uint32_t val; ++ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ++ struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); ++ ++ val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; ++ if (val == ITS_MASK) ++ return 1; ++ ++#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) ++ /* For PBL based platforms check the SB_EN bit in RCWSR */ ++ val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; ++ if (val == RCW_SB_EN_MASK) ++ return 1; ++#endif ++ ++#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) ++ /* For Non-PBL Platforms, check the Device Status register 2*/ ++ val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; ++ if (val != MPC85xx_PORDEVSR2_SBC_MASK) ++ return 1; ++ ++#endif ++ return 0; ++} ++ ++#ifndef CONFIG_SPL_BUILD ++int fsl_setenv_chain_of_trust(void) ++{ ++ /* Check Boot Mode ++ * If Boot Mode is Non-Secure, no changes are required ++ */ ++ if (fsl_check_boot_mode_secure() == 0) ++ return 0; ++ ++ /* If Boot mode is Secure, set the environment variables ++ * bootdelay = 0 (To disable Boot Prompt) ++ * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) ++ */ ++ env_set("bootdelay", "-2"); ++ ++#ifdef CONFIG_ARM ++ env_set("secureboot", "y"); ++#else ++ env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD); ++#endif ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_SPL_BUILD ++void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) ++{ ++ int res; ++ ++ /* ++ * Check Boot Mode ++ * If Boot Mode is Non-Secure, skip validation ++ */ ++ if (fsl_check_boot_mode_secure() == 0) ++ return; ++ ++ printf("SPL: Validating U-Boot image\n"); ++ ++#ifdef CONFIG_ADDR_MAP ++ init_addr_map(); ++#endif ++ ++#ifdef CONFIG_FSL_CORENET ++ if (pamu_init() < 0) ++ fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); ++#endif ++ ++#ifdef CONFIG_FSL_CAAM ++ if (sec_init() < 0) ++ fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT); ++#endif ++ ++/* ++ * dm_init_and_scan() is called as part of common SPL framework, so no ++ * need to call it again but in case of powerpc platforms which currently ++ * do not use common SPL framework, so need to call this function here. ++ */ ++#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) ++ dm_init_and_scan(true); ++#endif ++ res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, ++ &img_addr); ++ ++ if (res == 0) ++ printf("SPL: Validation of U-boot successful\n"); ++} ++ ++#ifdef CONFIG_SPL_FRAMEWORK ++/* Override weak funtion defined in SPL framework to enable validation ++ * of main u-boot image before jumping to u-boot image. ++ */ ++void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) ++{ ++ typedef void __noreturn (*image_entry_noargs_t)(void); ++ uint32_t hdr_addr; ++ ++ image_entry_noargs_t image_entry = ++ (image_entry_noargs_t)(unsigned long)spl_image->entry_point; ++ ++ hdr_addr = (spl_image->entry_point + spl_image->size - ++ CONFIG_U_BOOT_HDR_SIZE); ++ spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); ++ /* ++ * In case of failure in validation, spl_validate_uboot would ++ * not return back in case of Production environment with ITS=1. ++ * Thus U-Boot will not start. ++ * In Development environment (ITS=0 and SB_EN=1), the function ++ * may return back in case of non-fatal failures. ++ */ ++ ++ debug("image entry point: 0x%lX\n", spl_image->entry_point); ++ image_entry(); ++} ++#endif /* ifdef CONFIG_SPL_FRAMEWORK */ ++#endif /* ifdef CONFIG_SPL_BUILD */ +diff --git a/board/solidrun/common/fsl_validate.c b/board/solidrun/common/fsl_validate.c +new file mode 100644 +index 0000000000..2bf9d58746 +--- /dev/null ++++ b/board/solidrun/common/fsl_validate.c +@@ -0,0 +1,962 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015 Freescale Semiconductor, Inc. ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <fsl_validate.h> ++#include <fsl_secboot_err.h> ++#include <fsl_sfp.h> ++#include <fsl_sec.h> ++#include <command.h> ++#include <malloc.h> ++#include <u-boot/rsa-mod-exp.h> ++#include <hash.h> ++#include <fsl_secboot_err.h> ++#ifdef CONFIG_ARCH_LS1021A ++#include <asm/arch/immap_ls102xa.h> ++#endif ++ ++#define SHA256_BITS 256 ++#define SHA256_BYTES (256/8) ++#define SHA256_NIBBLES (256/4) ++#define NUM_HEX_CHARS (sizeof(ulong) * 2) ++ ++#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ ++ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ++ ((key_len) == 2 * KEY_SIZE_BYTES)) ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++/* Global data structure */ ++static struct fsl_secboot_glb glb; ++#endif ++ ++/* This array contains DER value for SHA-256 */ ++static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, ++ 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, ++ 0x04, 0x20 ++ }; ++ ++static u8 hash_val[SHA256_BYTES]; ++ ++#ifdef CONFIG_ESBC_HDR_LS ++/* New Barker Code for LS ESBC Header */ ++static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 }; ++#else ++static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; ++#endif ++ ++void branch_to_self(void) __attribute__ ((noreturn)); ++ ++/* ++ * This function will put core in infinite loop. ++ * This will be called when the ESBC can not proceed further due ++ * to some unknown errors. ++ */ ++void branch_to_self(void) ++{ ++ printf("Core is in infinite loop due to errors.\n"); ++self: ++ goto self; ++} ++ ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++static u32 check_ie(struct fsl_secboot_img_priv *img) ++{ ++ if (img->hdr.ie_flag & IE_FLAG_MASK) ++ return 1; ++ ++ return 0; ++} ++ ++/* This function returns the CSF Header Address of uboot ++ * For MPC85xx based platforms, the LAW mapping for NOR ++ * flash changes in uboot code. Hence the offset needs ++ * to be calculated and added to the new NOR flash base ++ * address ++ */ ++#if defined(CONFIG_MPC85xx) ++int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) ++{ ++ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ++ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); ++ u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); ++ u32 flash_addr, addr; ++ int found = 0; ++ int i = 0; ++ ++ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ++ flash_addr = flash_info[i].start[0]; ++ addr = flash_info[i].start[0] + csf_flash_offset; ++ if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { ++ debug("Barker found on addr %x\n", addr); ++ found = 1; ++ break; ++ } ++ } ++ ++ if (!found) ++ return -1; ++ ++ *csf_addr = addr; ++ *flash_base_addr = flash_addr; ++ ++ return 0; ++} ++#else ++/* For platforms like LS1020, correct flash address is present in ++ * the header. So the function reqturns flash base address as 0 ++ */ ++int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) ++{ ++ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); ++ u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); ++ ++ if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, ++ barker_code, ESBC_BARKER_LEN)) ++ return -1; ++ ++ *csf_addr = csf_hdr_addr; ++ *flash_base_addr = 0; ++ return 0; ++} ++#endif ++ ++#if defined(CONFIG_ESBC_HDR_LS) ++static int get_ie_info_addr(uintptr_t *ie_addr) ++{ ++ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); ++ /* For LS-CH3, the address of IE Table is ++ * stated in Scratch13 and scratch14 of DCFG. ++ * Bootrom validates this table while validating uboot. ++ * DCFG is LE*/ ++ *ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]); ++ *ie_addr = *ie_addr << 32; ++ *ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]); ++ return 0; ++} ++#else /* CONFIG_ESBC_HDR_LS */ ++static int get_ie_info_addr(uintptr_t *ie_addr) ++{ ++ struct fsl_secboot_img_hdr *hdr; ++ struct fsl_secboot_sg_table *sg_tbl; ++ u32 flash_base_addr, csf_addr; ++ ++ if (get_csf_base_addr(&csf_addr, &flash_base_addr)) ++ return -1; ++ ++ hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; ++ ++ /* For SoC's with Trust Architecture v1 with corenet bus ++ * the sg table field in CSF header has absolute address ++ * for sg table in memory. In other Trust Architecture, ++ * this field specifies the offset of sg table from the ++ * base address of CSF Header ++ */ ++#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) ++ sg_tbl = (struct fsl_secboot_sg_table *) ++ (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + ++ flash_base_addr); ++#else ++ sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + ++ (u32)hdr->psgtable); ++#endif ++ ++ /* IE Key Table is the first entry in the SG Table */ ++#if defined(CONFIG_MPC85xx) ++ *ie_addr = (uintptr_t)((sg_tbl->src_addr & ++ ~(CONFIG_SYS_PBI_FLASH_BASE)) + ++ flash_base_addr); ++#else ++ *ie_addr = (uintptr_t)sg_tbl->src_addr; ++#endif ++ ++ debug("IE Table address is %lx\n", *ie_addr); ++ return 0; ++} ++#endif /* CONFIG_ESBC_HDR_LS */ ++#endif ++ ++#ifdef CONFIG_KEY_REVOCATION ++/* This function checks srk_table_flag in header and set/reset srk_flag.*/ ++static u32 check_srk(struct fsl_secboot_img_priv *img) ++{ ++#ifdef CONFIG_ESBC_HDR_LS ++ /* In LS, No SRK Flag as SRK is always present if IE not present*/ ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++ return !check_ie(img); ++#endif ++ return 1; ++#else ++ if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) ++ return 1; ++ ++ return 0; ++#endif ++} ++ ++/* This function returns ospr's key_revoc values.*/ ++static u32 get_key_revoc(void) ++{ ++ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ++ return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> ++ OSPR_KEY_REVOC_SHIFT; ++} ++ ++/* This function checks if selected key is revoked or not.*/ ++static u32 is_key_revoked(u32 keynum, u32 rev_flag) ++{ ++ if (keynum == UNREVOCABLE_KEY) ++ return 0; ++ ++ if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag) ++ return 1; ++ ++ return 0; ++} ++ ++/* It read validates srk_table key lengths.*/ ++static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) ++{ ++ int i = 0; ++ u32 ret, key_num, key_revoc_flag, size; ++ struct fsl_secboot_img_hdr *hdr = &img->hdr; ++ void *esbc = (u8 *)(uintptr_t)img->ehdrloc; ++ ++ if ((hdr->len_kr.num_srk == 0) || ++ (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) ++ return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; ++ ++ key_num = hdr->len_kr.srk_sel; ++ if (key_num == 0 || key_num > hdr->len_kr.num_srk) ++ return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; ++ ++ /* Get revoc key from sfp */ ++ key_revoc_flag = get_key_revoc(); ++ ret = is_key_revoked(key_num, key_revoc_flag); ++ if (ret) ++ return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; ++ ++ size = hdr->len_kr.num_srk * sizeof(struct srk_table); ++ ++ memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); ++ ++ for (i = 0; i < hdr->len_kr.num_srk; i++) { ++ if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len)) ++ return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; ++ } ++ ++ img->key_len = img->srk_tbl[key_num - 1].key_len; ++ ++ memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), ++ img->key_len); ++ ++ return 0; ++} ++#endif ++ ++#ifndef CONFIG_ESBC_HDR_LS ++static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) ++{ ++ struct fsl_secboot_img_hdr *hdr = &img->hdr; ++ void *esbc = (u8 *)(uintptr_t)img->ehdrloc; ++ ++ /* check key length */ ++ if (!CHECK_KEY_LEN(hdr->key_len)) ++ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; ++ ++ memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); ++ ++ img->key_len = hdr->key_len; ++ ++ return 0; ++} ++#endif /* CONFIG_ESBC_HDR_LS */ ++ ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++ ++static void install_ie_tbl(uintptr_t ie_tbl_addr, ++ struct fsl_secboot_img_priv *img) ++{ ++ /* Copy IE tbl to Global Data */ ++ memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info)); ++ img->ie_addr = (uintptr_t)&glb.ie_tbl; ++ glb.ie_addr = img->ie_addr; ++} ++ ++static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) ++{ ++ struct fsl_secboot_img_hdr *hdr = &img->hdr; ++ u32 ie_key_len, ie_revoc_flag, ie_num; ++ struct ie_key_info *ie_info; ++ ++ if (!img->ie_addr) { ++ if (get_ie_info_addr(&img->ie_addr)) ++ return ERROR_IE_TABLE_NOT_FOUND; ++ else ++ install_ie_tbl(img->ie_addr, img); ++ } ++ ++ ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; ++ if (ie_info->num_keys == 0 || ie_info->num_keys > 32) ++ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; ++ ++ ie_num = hdr->ie_key_sel; ++ if (ie_num == 0 || ie_num > ie_info->num_keys) ++ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; ++ ++ ie_revoc_flag = ie_info->key_revok; ++ if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) ++ return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; ++ ++ ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; ++ ++ if (!CHECK_KEY_LEN(ie_key_len)) ++ return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; ++ ++ memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), ++ ie_key_len); ++ ++ img->key_len = ie_key_len; ++ return 0; ++} ++#endif ++ ++ ++/* This function return length of public key.*/ ++static inline u32 get_key_len(struct fsl_secboot_img_priv *img) ++{ ++ return img->key_len; ++} ++ ++/* ++ * Handles the ESBC uboot client header verification failure. ++ * This function handles all the errors which might occur in the ++ * parsing and checking of ESBC uboot client header. It will also ++ * set the error bits in the SEC_MON. ++ */ ++static void fsl_secboot_header_verification_failure(void) ++{ ++ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ++ ++ /* 29th bit of OSPR is ITS */ ++ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; ++ ++ if (its == 1) ++ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); ++ else ++ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); ++ ++ printf("Generating reset request\n"); ++ do_reset(NULL, 0, 0, NULL); ++ /* If reset doesn't coocur, halt execution */ ++ do_esbc_halt(NULL, 0, 0, NULL); ++} ++ ++/* ++ * Handles the ESBC uboot client image verification failure. ++ * This function handles all the errors which might occur in the ++ * public key hash comparison and signature verification of ++ * ESBC uboot client image. It will also ++ * set the error bits in the SEC_MON. ++ */ ++static void fsl_secboot_image_verification_failure(void) ++{ ++ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ++ ++ u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; ++ ++ if (its == 1) { ++ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); ++ ++ printf("Generating reset request\n"); ++ do_reset(NULL, 0, 0, NULL); ++ /* If reset doesn't coocur, halt execution */ ++ do_esbc_halt(NULL, 0, 0, NULL); ++ ++ } else { ++ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); ++ } ++} ++ ++static void fsl_secboot_bootscript_parse_failure(void) ++{ ++ fsl_secboot_header_verification_failure(); ++} ++ ++/* ++ * Handles the errors in esbc boot. ++ * This function handles all the errors which might occur in the ++ * esbc boot phase. It will call the appropriate api to log the ++ * errors and set the error bits in the SEC_MON. ++ */ ++void fsl_secboot_handle_error(int error) ++{ ++#ifndef CONFIG_SPL_BUILD ++ const struct fsl_secboot_errcode *e; ++ ++ for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; ++ e++) { ++ if (e->errcode == error) ++ printf("ERROR :: %x :: %s\n", error, e->name); ++ } ++#else ++ printf("ERROR :: %x\n", error); ++#endif ++ ++ /* If Boot Mode is secure, transition the SNVS state and issue ++ * reset based on type of failure and ITS setting. ++ * If Boot mode is non-secure, return from this function. ++ */ ++ if (fsl_check_boot_mode_secure() == 0) ++ return; ++ ++ switch (error) { ++ case ERROR_ESBC_CLIENT_HEADER_BARKER: ++ case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: ++ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN: ++ case ERROR_ESBC_CLIENT_HEADER_SIG_LEN: ++ case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN: ++ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1: ++ case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2: ++ case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: ++ case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: ++ case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: ++ case ERROR_KEY_TABLE_NOT_FOUND: ++#ifdef CONFIG_KEY_REVOCATION ++ case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: ++ case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: ++ case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM: ++ case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN: ++#endif ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++ /*@fallthrough@*/ ++ case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED: ++ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY: ++ case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM: ++ case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN: ++ case ERROR_IE_TABLE_NOT_FOUND: ++#endif ++ fsl_secboot_header_verification_failure(); ++ break; ++ case ERROR_ESBC_SEC_RESET: ++ case ERROR_ESBC_SEC_DEQ: ++ case ERROR_ESBC_SEC_ENQ: ++ case ERROR_ESBC_SEC_DEQ_TO: ++ case ERROR_ESBC_SEC_JOBQ_STATUS: ++ case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY: ++ case ERROR_ESBC_CLIENT_HASH_COMPARE_EM: ++ fsl_secboot_image_verification_failure(); ++ break; ++ case ERROR_ESBC_MISSING_BOOTM: ++ fsl_secboot_bootscript_parse_failure(); ++ break; ++ case ERROR_ESBC_WRONG_CMD: ++ default: ++ branch_to_self(); ++ break; ++ } ++} ++ ++static void fsl_secblk_handle_error(int error) ++{ ++ switch (error) { ++ case ERROR_ESBC_SEC_ENQ: ++ fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ); ++ break; ++ case ERROR_ESBC_SEC_DEQ: ++ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ); ++ break; ++ case ERROR_ESBC_SEC_DEQ_TO: ++ fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO); ++ break; ++ default: ++ printf("Job Queue Output status %x\n", error); ++ fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS); ++ break; ++ } ++} ++ ++/* ++ * Calculate hash of key obtained via offset present in ESBC uboot ++ * client hdr. This function calculates the hash of key which is obtained ++ * through offset present in ESBC uboot client header. ++ */ ++static int calc_img_key_hash(struct fsl_secboot_img_priv *img) ++{ ++ struct hash_algo *algo; ++ void *ctx; ++ int i, srk = 0; ++ int ret = 0; ++ const char *algo_name = "sha256"; ++ ++ /* Calculate hash of the esbc key */ ++ ret = hash_progressive_lookup_algo(algo_name, &algo); ++ if (ret) ++ return ret; ++ ++ ret = algo->hash_init(algo, &ctx); ++ if (ret) ++ return ret; ++ ++ /* Update hash for ESBC key */ ++#ifdef CONFIG_KEY_REVOCATION ++ if (check_srk(img)) { ++ ret = algo->hash_update(algo, ctx, ++ (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), ++ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); ++ srk = 1; ++ } ++#endif ++ if (!srk) ++ ret = algo->hash_update(algo, ctx, ++ img->img_key, img->key_len, 1); ++ if (ret) ++ return ret; ++ ++ /* Copy hash at destination buffer */ ++ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < SHA256_BYTES; i++) ++ img->img_key_hash[i] = hash_val[i]; ++ ++ return 0; ++} ++ ++/* ++ * Calculate hash of ESBC hdr and ESBC. This function calculates the ++ * single hash of ESBC header and ESBC image. If SG flag is on, all ++ * SG entries are also hashed alongwith the complete SG table. ++ */ ++static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) ++{ ++ struct hash_algo *algo; ++ void *ctx; ++ int ret = 0; ++ int key_hash = 0; ++ const char *algo_name = "sha256"; ++ ++ /* Calculate the hash of the ESBC */ ++ ret = hash_progressive_lookup_algo(algo_name, &algo); ++ if (ret) ++ return ret; ++ ++ ret = algo->hash_init(algo, &ctx); ++ /* Copy hash at destination buffer */ ++ if (ret) ++ return ret; ++ ++ /* Update hash for CSF Header */ ++ ret = algo->hash_update(algo, ctx, ++ (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); ++ if (ret) ++ return ret; ++ ++ /* Update the hash with that of srk table if srk flag is 1 ++ * If IE Table is selected, key is not added in the hash ++ * If neither srk table nor IE key table available, add key ++ * from header in the hash calculation ++ */ ++#ifdef CONFIG_KEY_REVOCATION ++ if (check_srk(img)) { ++ ret = algo->hash_update(algo, ctx, ++ (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), ++ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); ++ key_hash = 1; ++ } ++#endif ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++ if (!key_hash && check_ie(img)) ++ key_hash = 1; ++#endif ++#ifndef CONFIG_ESBC_HDR_LS ++/* No single key support in LS ESBC header */ ++ if (!key_hash) { ++ ret = algo->hash_update(algo, ctx, ++ img->img_key, img->hdr.key_len, 0); ++ key_hash = 1; ++ } ++#endif ++ if (ret) ++ return ret; ++ if (!key_hash) ++ return ERROR_KEY_TABLE_NOT_FOUND; ++ ++ /* Update hash for actual Image */ ++ ret = algo->hash_update(algo, ctx, ++ (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); ++ if (ret) ++ return ret; ++ ++ /* Copy hash at destination buffer */ ++ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++/* ++ * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the ++ * pointers for padding, DER value and hash. And finally, constructs EM' ++ * which includes hash of complete CSF header and ESBC image. If SG flag ++ * is on, hash of SG table and entries is also included. ++ */ ++static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img) ++{ ++ /* ++ * RSA PKCSv1.5 encoding format for encoded message is below ++ * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash ++ * PS is Padding String ++ * DER is DER value for SHA-256 ++ * Hash is SHA-256 hash ++ * ********************************************************* ++ * representative points to first byte of EM initially and is ++ * filled with 0x0 ++ * representative is incremented by 1 and second byte is filled ++ * with 0x1 ++ * padding points to third byte of EM ++ * digest points to full length of EM - 32 bytes ++ * hash_id (DER value) points to 19 bytes before pDigest ++ * separator is one byte which separates padding and DER ++ */ ++ ++ size_t len; ++ u8 *representative; ++ u8 *padding, *digest; ++ u8 *hash_id, *separator; ++ int i; ++ ++ len = (get_key_len(img) / 2) - 1; ++ representative = img->img_encoded_hash_second; ++ representative[0] = 0; ++ representative[1] = 1; /* block type 1 */ ++ ++ padding = &representative[2]; ++ digest = &representative[1] + len - 32; ++ hash_id = digest - sizeof(hash_identifier); ++ separator = hash_id - 1; ++ ++ /* fill padding area pointed by padding with 0xff */ ++ memset(padding, 0xff, separator - padding); ++ ++ /* fill byte pointed by separator */ ++ *separator = 0; ++ ++ /* fill SHA-256 DER value pointed by HashId */ ++ memcpy(hash_id, hash_identifier, sizeof(hash_identifier)); ++ ++ /* fill hash pointed by Digest */ ++ for (i = 0; i < SHA256_BYTES; i++) ++ digest[i] = hash_val[i]; ++} ++ ++/* ++ * Reads and validates the ESBC client header. ++ * This function reads key and signature from the ESBC client header. ++ * If Scatter/Gather flag is on, lengths and offsets of images ++ * present as SG entries are also read. This function also checks ++ * whether the header is valid or not. ++ */ ++static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) ++{ ++ struct fsl_secboot_img_hdr *hdr = &img->hdr; ++ void *esbc = (u8 *)(uintptr_t)img->ehdrloc; ++ u8 *k, *s; ++ u32 ret = 0; ++ ++ int key_found = 0; ++ ++ /* check barker code */ ++ if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) ++ return ERROR_ESBC_CLIENT_HEADER_BARKER; ++ ++ /* If Image Address is not passed as argument to function, ++ * then Address and Size must be read from the Header. ++ */ ++ if (*(img->img_addr_ptr) == 0) { ++ #ifdef CONFIG_ESBC_ADDR_64BIT ++ *(img->img_addr_ptr) = hdr->pimg64; ++ #else ++ *(img->img_addr_ptr) = hdr->pimg; ++ #endif ++ } ++ ++ if (!hdr->img_size) ++ return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; ++ ++ img->img_size = hdr->img_size; ++ ++ /* Key checking*/ ++#ifdef CONFIG_KEY_REVOCATION ++ if (check_srk(img)) { ++ ret = read_validate_srk_tbl(img); ++ if (ret != 0) ++ return ret; ++ key_found = 1; ++ } ++#endif ++ ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++ if (!key_found && check_ie(img)) { ++ ret = read_validate_ie_tbl(img); ++ if (ret != 0) ++ return ret; ++ key_found = 1; ++ } ++#endif ++#ifndef CONFIG_ESBC_HDR_LS ++/* Single Key Feature not available in LS ESBC Header */ ++ if (key_found == 0) { ++ ret = read_validate_single_key(img); ++ if (ret != 0) ++ return ret; ++ key_found = 1; ++ } ++#endif ++ if (!key_found) ++ return ERROR_KEY_TABLE_NOT_FOUND; ++ ++ /* check signaure */ ++ if (get_key_len(img) == 2 * hdr->sign_len) { ++ /* check signature length */ ++ if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) || ++ (hdr->sign_len == KEY_SIZE_BYTES / 2) || ++ (hdr->sign_len == KEY_SIZE_BYTES))) ++ return ERROR_ESBC_CLIENT_HEADER_SIG_LEN; ++ } else { ++ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN; ++ } ++ ++ memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); ++/* No SG support in LS-CH3 */ ++#ifndef CONFIG_ESBC_HDR_LS ++ /* No SG support */ ++ if (hdr->sg_flag) ++ return ERROR_ESBC_CLIENT_HEADER_SG; ++#endif ++ ++ /* modulus most significant bit should be set */ ++ k = (u8 *)&img->img_key; ++ ++ if ((k[0] & 0x80) == 0) ++ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1; ++ ++ /* modulus value should be odd */ ++ if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0) ++ return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2; ++ ++ /* Check signature value < modulus value */ ++ s = (u8 *)&img->img_sign; ++ ++ if (!(memcmp(s, k, hdr->sign_len) < 0)) ++ return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD; ++ ++ return ESBC_VALID_HDR; ++} ++ ++static inline int str2longbe(const char *p, ulong *num) ++{ ++ char *endptr; ++ ulong tmp; ++ ++ if (!p) { ++ return 0; ++ } else { ++ tmp = simple_strtoul(p, &endptr, 16); ++ if (sizeof(ulong) == 4) ++ *num = cpu_to_be32(tmp); ++ else ++ *num = cpu_to_be64(tmp); ++ } ++ ++ return *p != '\0' && *endptr == '\0'; ++} ++/* Function to calculate the ESBC Image Hash ++ * and hash from Digital signature. ++ * The Two hash's are compared to yield the ++ * result of signature validation. ++ */ ++static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) ++{ ++ int ret; ++ uint32_t key_len; ++ struct key_prop prop; ++#if !defined(USE_HOSTCC) ++ struct udevice *mod_exp_dev; ++#endif ++ ret = calc_esbchdr_esbc_hash(img); ++ if (ret) ++ return ret; ++ ++ /* Construct encoded hash EM' wrt PKCSv1.5 */ ++ construct_img_encoded_hash_second(img); ++ ++ /* Fill prop structure for public key */ ++ memset(&prop, 0, sizeof(struct key_prop)); ++ key_len = get_key_len(img) / 2; ++ prop.modulus = img->img_key; ++ prop.public_exponent = img->img_key + key_len; ++ prop.num_bits = key_len * 8; ++ prop.exp_len = key_len; ++ ++ ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); ++ if (ret) { ++ printf("RSA: Can't find Modular Exp implementation\n"); ++ return -EINVAL; ++ } ++ ++ ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, ++ &prop, img->img_encoded_hash); ++ if (ret) ++ return ret; ++ ++ /* ++ * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 ++ * memcmp returns zero on success ++ * memcmp returns non-zero on failure ++ */ ++ ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, ++ img->hdr.sign_len); ++ ++ if (ret) ++ return ERROR_ESBC_CLIENT_HASH_COMPARE_EM; ++ ++ return 0; ++} ++/* Function to initialize img priv and global data structure ++ */ ++static int secboot_init(struct fsl_secboot_img_priv **img_ptr) ++{ ++ *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv)); ++ ++ struct fsl_secboot_img_priv *img = *img_ptr; ++ ++ if (!img) ++ return -ENOMEM; ++ memset(img, 0, sizeof(struct fsl_secboot_img_priv)); ++ ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++ if (glb.ie_addr) ++ img->ie_addr = glb.ie_addr; ++#endif ++ return 0; ++} ++ ++ ++/* haddr - Address of the header of image to be validated. ++ * arg_hash_str - Option hash string. If provided, this ++ * overrides the key hash in the SFP fuses. ++ * img_addr_ptr - Optional pointer to address of image to be validated. ++ * If non zero addr, this overrides the addr of image in header, ++ * otherwise updated to image addr in header. ++ * Acts as both input and output of function. ++ * This pointer shouldn't be NULL. ++ */ ++int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, ++ uintptr_t *img_addr_ptr) ++{ ++ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ++ ulong hash[SHA256_BYTES/sizeof(ulong)]; ++ char hash_str[NUM_HEX_CHARS + 1]; ++ struct fsl_secboot_img_priv *img; ++ struct fsl_secboot_img_hdr *hdr; ++ void *esbc; ++ int ret, i, hash_cmd = 0; ++ u32 srk_hash[8]; ++ ++ if (arg_hash_str != NULL) { ++ const char *cp = arg_hash_str; ++ int i = 0; ++ ++ if (*cp == '0' && *(cp + 1) == 'x') ++ cp += 2; ++ ++ /* The input string expected is in hex, where ++ * each 4 bits would be represented by a hex ++ * sha256 hash is 256 bits long, which would mean ++ * num of characters = 256 / 4 ++ */ ++ if (strlen(cp) != SHA256_NIBBLES) { ++ printf("%s is not a 256 bits hex string as expected\n", ++ arg_hash_str); ++ return -1; ++ } ++ ++ for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) { ++ strncpy(hash_str, cp + (i * NUM_HEX_CHARS), ++ NUM_HEX_CHARS); ++ hash_str[NUM_HEX_CHARS] = '\0'; ++ if (!str2longbe(hash_str, &hash[i])) { ++ printf("%s is not a 256 bits hex string ", ++ arg_hash_str); ++ return -1; ++ } ++ } ++ ++ hash_cmd = 1; ++ } ++ ++ ret = secboot_init(&img); ++ if (ret) ++ goto exit; ++ ++ /* Update the information in Private Struct */ ++ hdr = &img->hdr; ++ img->ehdrloc = haddr; ++ img->img_addr_ptr = img_addr_ptr; ++ esbc = (u8 *)img->ehdrloc; ++ ++ memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); ++ ++ /* read and validate esbc header */ ++ ret = read_validate_esbc_client_header(img); ++ ++ if (ret != ESBC_VALID_HDR) { ++ fsl_secboot_handle_error(ret); ++ goto exit; ++ } ++ ++ /* SRKH present in SFP */ ++ for (i = 0; i < NUM_SRKH_REGS; i++) ++ srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]); ++ ++ /* ++ * Calculate hash of key obtained via offset present in ++ * ESBC uboot client hdr ++ */ ++ ret = calc_img_key_hash(img); ++ if (ret) { ++ fsl_secblk_handle_error(ret); ++ goto exit; ++ } ++ ++ /* Compare hash obtained above with SRK hash present in SFP */ ++ if (hash_cmd) ++ ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES); ++ else ++ ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES); ++ ++#if defined(CONFIG_FSL_ISBC_KEY_EXT) ++ if (!hash_cmd && check_ie(img)) ++ ret = 0; ++#endif ++ ++ if (ret != 0) { ++ fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY); ++ goto exit; ++ } ++ ++ ret = calculate_cmp_img_sig(img); ++ if (ret) { ++ fsl_secboot_handle_error(ret); ++ goto exit; ++ } ++ ++exit: ++ /* Free Img as it was malloc'ed*/ ++ free(img); ++ return ret; ++} +diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c +new file mode 100644 +index 0000000000..cc81e80c37 +--- /dev/null ++++ b/board/solidrun/common/vid.c +@@ -0,0 +1,330 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2014 Freescale Semiconductor, Inc. ++ * Copyright 2018 NXP ++ */ ++#include <common.h> ++#include <command.h> ++#include <i2c.h> ++#include <asm/io.h> ++#ifdef CONFIG_FSL_LSCH2 ++#include <asm/arch/immap_lsch2.h> ++#elif defined(CONFIG_FSL_LSCH3) ++#include <asm/arch/immap_lsch3.h> ++#else ++#include <asm/immap_85xx.h> ++#endif ++#include "vid.h" ++ ++int __weak i2c_multiplexer_select_vid_channel(u8 channel) ++{ ++ return 0; ++} ++ ++/* ++ * Compensate for a board specific voltage drop between regulator and SoC ++ * return a value in mV ++ */ ++int __weak board_vdd_drop_compensation(void) ++{ ++ return 0; ++} ++ ++/* ++ * Board specific settings for specific voltage value ++ */ ++int __weak board_adjust_vdd(int vdd) ++{ ++ return 0; ++} ++ ++/* Maximum loop count waiting for new voltage to take effect */ ++#define MAX_LOOP_WAIT_NEW_VOL 100 ++/* Maximum loop count waiting for the voltage to be stable */ ++#define MAX_LOOP_WAIT_VOL_STABLE 100 ++/* ++ * read_voltage from sensor on I2C bus ++ * We use average of 4 readings, waiting for WAIT_FOR_ADC before ++ * another reading ++ */ ++#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ ++ ++/* If an INA220 chip is available, we can use it to read back the voltage ++ * as it may have a higher accuracy than the IR chip for the same purpose ++ */ ++#ifdef CONFIG_VOL_MONITOR_INA220 ++#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ ++#define ADC_MIN_ACCURACY 4 ++#else ++#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */ ++#define ADC_MIN_ACCURACY 4 ++#endif ++ ++/* read the current value of the LTC Regulator Voltage */ ++static int read_voltage_from_LTC(int i2caddress) ++{ ++ int ret, vcode = 0; ++ u8 chan = PWM_CHANNEL0; ++ ++ /* select the PAGE 0 using PMBus commands PAGE for VDD*/ ++ ret = i2c_write(I2C_VOL_MONITOR_ADDR, ++ PMBUS_CMD_PAGE, 1, &chan, 1); ++ if (ret) { ++ printf("VID: failed to select VDD Page 0\n"); ++ return ret; ++ } ++ ++ /*read the output voltage using PMBus command READ_VOUT*/ ++ ret = i2c_read(I2C_VOL_MONITOR_ADDR, ++ PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); ++ if (ret) { ++ printf("VID: failed to read the volatge\n"); ++ return ret; ++ } ++ ++ /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */ ++ vcode = DIV_ROUND_UP(vcode * 1000, 4096); ++ ++ return vcode; ++} ++ ++static int read_voltage(int i2caddress) ++{ ++ int voltage_read; ++ voltage_read = read_voltage_from_LTC(i2caddress); ++ return voltage_read; ++} ++ ++/* this function sets the VDD and returns the value set */ ++static int set_voltage_to_LTC(int i2caddress, int vdd) ++{ ++ int ret, vdd_last, vdd_target = vdd; ++ int count = 100, temp = 0; ++ ++ /* Scale up to the LTC resolution is 1/4096V */ ++ vdd = (vdd * 4096) / 1000; ++ ++ /* 5-byte buffer which needs to be sent following the ++ * PMBus command PAGE_PLUS_WRITE. ++ */ ++ u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, ++ vdd & 0xFF, (vdd & 0xFF00) >> 8}; ++ ++ /* Write the desired voltage code to the regulator */ ++ ret = i2c_write(I2C_VOL_MONITOR_ADDR, ++ PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); ++ if (ret) { ++ printf("VID: I2C failed to write to the volatge regulator\n"); ++ return -1; ++ } ++ ++ /* Wait for the volatge to get to the desired value */ ++ do { ++ vdd_last = read_voltage_from_LTC(i2caddress); ++ if (vdd_last < 0) { ++ printf("VID: Couldn't read sensor abort VID adjust\n"); ++ return -1; ++ } ++ count--; ++ temp = vdd_last - vdd_target; ++ } while ((abs(temp) > 2) && (count > 0)); ++ ++ return vdd_last; ++} ++ ++static int set_voltage(int i2caddress, int vdd) ++{ ++ int vdd_last = -1; ++ ++ vdd_last = set_voltage_to_LTC(i2caddress, vdd); ++ return vdd_last; ++} ++ ++int adjust_vdd(ulong vdd_override) ++{ ++ int re_enable = disable_interrupts(); ++ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); ++ u32 fusesr; ++ u8 vid; ++ int vdd_target, vdd_current, vdd_last; ++ int ret, i2caddress; ++ unsigned long vdd_string_override; ++ char *vdd_string; ++ static const u16 vdd[32] = { ++ 8250, ++ 7875, ++ 7750, ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 8000, ++ 8125, ++ 8250, ++ 0, /* reserved */ ++ 8500, ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ }; ++ struct vdd_drive { ++ u8 vid; ++ unsigned voltage; ++ }; ++ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); ++ if (ret) { ++ debug("VID: I2C failed to switch channel\n"); ++ ret = -1; ++ goto exit; ++ } ++ /* get the voltage ID from fuse status register */ ++ fusesr = in_le32(&gur->dcfg_fusesr); ++ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & ++ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; ++ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { ++ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & ++ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; ++ } ++ vdd_target = vdd[vid]; ++ printf ("vid FUSE index %d (vdd_target = %d)\n",vid,vdd_target); ++ ++ /* check override variable for overriding VDD */ ++ vdd_string = env_get(CONFIG_VID_FLS_ENV); ++ if (vdd_override == 0 && vdd_string && ++ !strict_strtoul(vdd_string, 10, &vdd_string_override)) ++ vdd_override = vdd_string_override; ++ ++ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { ++ vdd_target = vdd_override * 10; /* convert to 1/10 mV */ ++ debug("VDD override is %lu\n", vdd_override); ++ } else if (vdd_override != 0) { ++ printf("Invalid value.\n"); ++ } ++ ++ /* divide and round up by 10 to get a value in mV */ ++ vdd_target = DIV_ROUND_UP(vdd_target, 10); ++ if (vdd_target == 0) { ++ debug("VID: VID not used\n"); ++ ret = 0; ++ goto exit; ++ } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) { ++ /* Check vdd_target is in valid range */ ++ printf("VID: Target VID %d mV is not in range.\n", ++ vdd_target); ++ ret = -1; ++ goto exit; ++ } else { ++ debug("VID: vid = %d mV\n", vdd_target); ++ } ++ ++ /* ++ * Read voltage monitor to check real voltage. ++ */ ++ vdd_last = read_voltage(i2caddress); ++ if (vdd_last < 0) { ++ printf("VID: Couldn't read sensor abort VID adjustment\n"); ++ ret = -1; ++ goto exit; ++ } ++ vdd_current = vdd_last; ++ debug("VID: Core voltage is currently at %d mV\n", vdd_last); ++ ++ /* Set the target voltage */ ++ vdd_last = vdd_current = set_voltage(i2caddress, vdd_target); ++ if (board_adjust_vdd(vdd_target) < 0) { ++ ret = -1; ++ goto exit; ++ } ++ ++ if (vdd_last > 0) ++ printf("VID: Core voltage after adjustment is at %d mV\n", ++ vdd_last); ++ else ++ ret = -1; ++exit: ++ if (re_enable) ++ enable_interrupts(); ++ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); ++ return ret; ++} ++ ++static int print_vdd(void) ++{ ++ int vdd_last, ret, i2caddress; ++ ++ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); ++ if (ret) { ++ debug("VID : I2c failed to switch channel\n"); ++ return -1; ++ } ++ /* ++ * Read voltage monitor to check real voltage. ++ */ ++ vdd_last = read_voltage(i2caddress); ++ if (vdd_last < 0) { ++ printf("VID: Couldn't read sensor abort VID adjustment\n"); ++ goto exit; ++ } ++ printf("VID: Core voltage is at %d mV\n", vdd_last); ++exit: ++ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); ++ ++ return ret < 0 ? -1 : 0; ++ ++} ++ ++static int do_vdd_override(cmd_tbl_t *cmdtp, ++ int flag, int argc, ++ char * const argv[]) ++{ ++ ulong override; ++ ++ if (argc < 2) ++ return CMD_RET_USAGE; ++ ++ if (!strict_strtoul(argv[1], 10, &override)) ++ adjust_vdd(override); /* the value is checked by callee */ ++ else ++ return CMD_RET_USAGE; ++ return 0; ++} ++ ++static int do_vdd_read(cmd_tbl_t *cmdtp, ++ int flag, int argc, ++ char * const argv[]) ++{ ++ if (argc < 1) ++ return CMD_RET_USAGE; ++ print_vdd(); ++ ++ return 0; ++} ++ ++U_BOOT_CMD( ++ vdd_override, 2, 0, do_vdd_override, ++ "override VDD", ++ " - override with the voltage specified in mV, eg. 1050" ++); ++ ++U_BOOT_CMD( ++ vdd_read, 1, 0, do_vdd_read, ++ "read VDD", ++ " - Read the voltage specified in mV" ++) +diff --git a/board/solidrun/common/vid.h b/board/solidrun/common/vid.h +new file mode 100644 +index 0000000000..99778e9a93 +--- /dev/null ++++ b/board/solidrun/common/vid.h +@@ -0,0 +1,23 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2014 Freescale Semiconductor, Inc. ++ */ ++ ++#ifndef __VID_H_ ++#define __VID_H_ ++ ++#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A ++#define IR36021_LOOP1_VOUT_OFFSET 0x9A ++#define IR36021_MFR_ID_OFFSET 0x92 ++#define IR36021_MFR_ID 0x43 ++#define IR36021_INTEL_MODE_OOFSET 0x14 ++#define IR36021_MODE_MASK 0x20 ++#define IR36021_INTEL_MODE 0x00 ++#define IR36021_AMD_MODE 0x20 ++ ++/* step the IR regulator in 5mV increments */ ++#define IR_VDD_STEP_DOWN 5 ++#define IR_VDD_STEP_UP 5 ++int adjust_vdd(ulong vdd_override); ++ ++#endif /* __VID_H_ */ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch new file mode 100644 index 00000000..51acc55b --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch @@ -0,0 +1,91 @@ +From bd96fd21fafd7560dba1d5a6f893e4a7d0b7ee74 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 13:37:22 +0300 +Subject: [PATCH 05/17] armv8: lx2160acex7: lx2160acex device tree + +Based on NXP's LX2160ARDB device tree; it defines - +1. MX35X based SPI flash +2. SDHC0 (SD card) and SDHC1 (eMMC) +3. 4 SATA ports that depending on SERDES configuration they can get +connected to external SATA drives + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + arch/arm/dts/fsl-lx2160a-cex7.dts | 63 +++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts + +diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts +new file mode 100644 +index 0000000000..4fbcaafb0e +--- /dev/null ++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts +@@ -0,0 +1,63 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR X11 ++/* ++ * SolidRun LX2160ACEX7 device tree source ++ * ++ * Author: Rabeeh Khoury <rabeeh@solid-run.com> ++ * ++ * Copyright 2019 SolidRun ltd. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "fsl-lx2160a.dtsi" ++ ++/ { ++ model = "SolidRun LX2160ACEX7 COM express type 7 based board"; ++ compatible = "fsl,lx2160acex7", "fsl,lx2160a"; ++ ++ aliases { ++ spi0 = &fspi; ++ }; ++}; ++ ++&fspi { ++ bus-num = <0>; ++ status = "okay"; ++ ++ qflash0: MT35XU512ABA1G12@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-flash"; ++ spi-max-frequency = <50000000>; ++ reg = <0>; ++ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ ++ fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */ ++ fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */ ++ }; ++ ++}; ++ ++&esdhc0 { ++ status = "okay"; ++}; ++ ++&esdhc1 { ++ status = "okay"; ++}; ++ ++&sata0 { ++ status = "okay"; ++}; ++ ++&sata1 { ++ status = "okay"; ++}; ++ ++&sata2 { ++ status = "okay"; ++}; ++ ++&sata3 { ++ status = "okay"; ++}; +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch new file mode 100644 index 00000000..c38abbf9 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch @@ -0,0 +1,519 @@ +From c42a926fb0ff087b8c5cb774a67fb64aa1a566ce Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 13:45:24 +0300 +Subject: [PATCH 06/17] armv8: lx2160acex7: board support files + +The lx2160acex7 board support files does the following - +1. Initializes 1GBps PHY address according to SERDES1 block config. +2. Sets uart0 as the console +3. Sets EMC2301 PWM fan controller to it's default value +4. Misc FDT fixups prior to booting Linux + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + board/solidrun/lx2160a/Kconfig | 22 ++ + board/solidrun/lx2160a/MAINTAINERS | 8 + + board/solidrun/lx2160a/Makefile | 9 + + board/solidrun/lx2160a/ddr.c | 20 ++ + board/solidrun/lx2160a/eth_lx2160acex7.c | 104 ++++++++ + board/solidrun/lx2160a/lx2160a.c | 288 +++++++++++++++++++++++ + 6 files changed, 451 insertions(+) + create mode 100644 board/solidrun/lx2160a/Kconfig + create mode 100644 board/solidrun/lx2160a/MAINTAINERS + create mode 100644 board/solidrun/lx2160a/Makefile + create mode 100644 board/solidrun/lx2160a/ddr.c + create mode 100644 board/solidrun/lx2160a/eth_lx2160acex7.c + create mode 100644 board/solidrun/lx2160a/lx2160a.c + +diff --git a/board/solidrun/lx2160a/Kconfig b/board/solidrun/lx2160a/Kconfig +new file mode 100644 +index 0000000000..85abac9bfc +--- /dev/null ++++ b/board/solidrun/lx2160a/Kconfig +@@ -0,0 +1,22 @@ ++if TARGET_LX2160ACEX7 ++ ++config SYS_BOARD ++ default "lx2160a" ++ ++config SYS_VENDOR ++ default "solidrun" ++ ++config SYS_SOC ++ default "fsl-layerscape" ++ ++config SYS_CONFIG_NAME ++ default "lx2160acex7" ++ ++config EMC2301 ++ bool "Fan controller" ++ help ++ Enable the EMC2301 fan controller for configuration of fan ++ speed. ++ ++source "board/freescale/common/Kconfig" ++endif +diff --git a/board/solidrun/lx2160a/MAINTAINERS b/board/solidrun/lx2160a/MAINTAINERS +new file mode 100644 +index 0000000000..688ff66afa +--- /dev/null ++++ b/board/solidrun/lx2160a/MAINTAINERS +@@ -0,0 +1,8 @@ ++LX2160ACEX7 BOARD ++M: Rabeeh Khoury <rabeeh@solid-run.com> ++S: Maintained ++F: board/solidrun/lx2160a/ ++F: include/configs/lx2160a_common.h ++F: include/configs/lx2160acex7.h ++F: configs/lx2160acex7_tfa_defconfig ++F: arch/arm/dts/fsl-lx2160a-cex7.dts +diff --git a/board/solidrun/lx2160a/Makefile b/board/solidrun/lx2160a/Makefile +new file mode 100644 +index 0000000000..c92266f322 +--- /dev/null ++++ b/board/solidrun/lx2160a/Makefile +@@ -0,0 +1,9 @@ ++# ++# Copyright 2019 SolidRun ltd. ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += lx2160a.o ++obj-y += ddr.o ++obj-$(CONFIG_TARGET_LX2160ACEX7) += eth_lx2160acex7.o +diff --git a/board/solidrun/lx2160a/ddr.c b/board/solidrun/lx2160a/ddr.c +new file mode 100644 +index 0000000000..9c7bd10475 +--- /dev/null ++++ b/board/solidrun/lx2160a/ddr.c +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2019 SolidRun ltd. ++ */ ++ ++#include <common.h> ++#include <fsl_ddr_sdram.h> ++#include <fsl_ddr_dimm_params.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int fsl_initdram(void) ++{ ++ gd->ram_size = tfa_get_dram_size(); ++ ++ if (!gd->ram_size) ++ gd->ram_size = fsl_ddr_sdram_size(); ++ ++ return 0; ++} +diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c +new file mode 100644 +index 0000000000..97e414838f +--- /dev/null ++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c +@@ -0,0 +1,104 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2019 SolidRun ltd. ++ * ++ */ ++ ++#include <common.h> ++#include <command.h> ++#include <netdev.h> ++#include <malloc.h> ++#include <fsl_mdio.h> ++#include <miiphy.h> ++#include <phy.h> ++#include <fm_eth.h> ++#include <asm/io.h> ++#include <exports.h> ++#include <asm/arch/fsl_serdes.h> ++#include <fsl-mc/fsl_mc.h> ++#include <fsl-mc/ldpaa_wriop.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int board_eth_init(bd_t *bis) ++{ ++#if defined(CONFIG_FSL_MC_ENET) ++ struct memac_mdio_info mdio_info; ++ struct memac_mdio_controller *reg; ++ int i, interface; ++ struct mii_dev *dev; ++ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); ++ u32 srds_s1; ++ ++ srds_s1 = in_le32(&gur->rcwsr[28]) & ++ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; ++ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; ++ ++ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; ++ mdio_info.regs = reg; ++ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; ++ ++ /* Register the EMI 1 */ ++ fm_memac_mdio_init(bis, &mdio_info); ++ ++ wriop_set_phy_address(WRIOP1_DPMAC17, 0, ++ RGMII_PHY_ADDR1); ++ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; ++ switch (srds_s1) { ++ case 3: ++ case 5: ++ case 8: ++ case 13: ++ case 14: ++ case 15: ++ case 17: ++ case 20: ++ case 23: ++ wriop_set_phy_address(WRIOP1_DPMAC17, 0, ++ RGMII_PHY_ADDR1); ++ break; ++ ++ default: ++ printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n", ++ srds_s1); ++ goto next; ++ } ++ for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) { ++ interface = wriop_get_enet_if(i); ++ switch (interface) { ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); ++ wriop_set_mdio(i, dev); ++ break; ++ default: ++ break; ++ } ++ } ++ ++next: ++ cpu_eth_init(bis); ++#endif /* CONFIG_FSL_MC_ENET */ ++ ++ return pci_eth_init(bis); ++} ++ ++#if defined(CONFIG_RESET_PHY_R) ++void reset_phy(void) ++{ ++#if defined(CONFIG_FSL_MC_ENET) ++ mc_env_boot(); ++#endif ++} ++#endif /* CONFIG_RESET_PHY_R */ ++ ++int fdt_fixup_board_phy(void *fdt) ++{ ++ int mdio_offset; ++ int ret; ++ struct mii_dev *dev; ++ ++ ret = 0; ++ ++ return ret; ++} +diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c +new file mode 100644 +index 0000000000..b0d9f1012e +--- /dev/null ++++ b/board/solidrun/lx2160a/lx2160a.c +@@ -0,0 +1,288 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2019 SolidRun ltd. ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <dm/platform_data/serial_pl01x.h> ++#include <i2c.h> ++#include <malloc.h> ++#include <errno.h> ++#include <netdev.h> ++#include <fsl_ddr.h> ++#include <fsl_sec.h> ++#include <asm/io.h> ++#include <fdt_support.h> ++#include <linux/libfdt.h> ++#include <fsl-mc/fsl_mc.h> ++#include <environment.h> ++#include <efi_loader.h> ++#include <asm/arch/mmu.h> ++#include <hwconfig.h> ++#include <asm/arch/fsl_serdes.h> ++#include <asm/arch/soc.h> ++#include "../../freescale/common/vid.h" ++#include <fsl_immap.h> ++ ++#ifdef CONFIG_EMC2301 ++#include "../common/emc2301.h" ++#endif ++ ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++static struct pl01x_serial_platdata serial0 = { ++#if CONFIG_CONS_INDEX == 0 ++ .base = CONFIG_SYS_SERIAL0, ++#elif CONFIG_CONS_INDEX == 1 ++ .base = CONFIG_SYS_SERIAL1, ++#else ++#error "Unsupported console index value." ++#endif ++ .type = TYPE_PL011, ++}; ++ ++U_BOOT_DEVICE(nxp_serial0) = { ++ .name = "serial_pl01x", ++ .platdata = &serial0, ++}; ++ ++static struct pl01x_serial_platdata serial1 = { ++ .base = CONFIG_SYS_SERIAL1, ++ .type = TYPE_PL011, ++}; ++ ++U_BOOT_DEVICE(nxp_serial1) = { ++ .name = "serial_pl01x", ++ .platdata = &serial1, ++}; ++ ++int select_i2c_ch_pca9547(u8 ch) ++{ ++ int ret; ++ ++ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); ++ if (ret) { ++ puts("PCA: failed to select proper channel\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void uart_get_clock(void) ++{ ++ serial0.clock = get_serial_clock(); ++ serial1.clock = get_serial_clock(); ++} ++ ++int board_early_init_f(void) ++{ ++#ifdef CONFIG_SYS_I2C_EARLY_INIT ++ i2c_early_init_f(); ++#endif ++ /* get required clock for UART IP */ ++ uart_get_clock(); ++ ++#ifdef CONFIG_EMC2301 ++ select_i2c_ch_pca9547(I2C_MUX_CH_EMC2301); ++ emc2301_init(); ++ set_fan_speed(I2C_EMC2301_PWM); ++ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); ++#endif ++ fsl_lsch3_early_init_f(); ++ return 0; ++} ++ ++#ifdef CONFIG_OF_BOARD_FIXUP ++int board_fix_fdt(void *fdt) ++{ ++ return 0; ++} ++#endif ++ ++int esdhc_status_fixup(void *blob, const char *compat) ++{ ++ /* Enable both esdhc DT nodes for LX2160ARDB */ ++ do_fixup_by_compat(blob, compat, "status", "okay", ++ sizeof("okay"), 1); ++ return 0; ++} ++ ++#if defined(CONFIG_VID) ++int i2c_multiplexer_select_vid_channel(u8 channel) ++{ ++ return select_i2c_ch_pca9547(channel); ++} ++ ++#endif ++ ++int checkboard(void) ++{ ++ enum boot_src src = get_boot_src(); ++ char buf[64]; ++ cpu_name(buf); ++ printf("Board: %s-CEX7, ", buf); ++ ++ if (src == BOOT_SOURCE_SD_MMC) { ++ puts("SD\n"); ++ } ++ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n"); ++ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); ++ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n"); ++ return 0; ++} ++ ++int config_board_mux(void) ++{ ++ return 0; ++} ++ ++unsigned long get_board_sys_clk(void) ++{ ++ return 100000000; ++} ++ ++unsigned long get_board_ddr_clk(void) ++{ ++ return 100000000; ++} ++ ++int board_init(void) ++{ ++#ifdef CONFIG_ENV_IS_NOWHERE ++ gd->env_addr = (ulong)&default_environment[0]; ++#endif ++ ++ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); ++ ++#ifdef CONFIG_FSL_CAAM ++ sec_init(); ++#endif ++ ++ return 0; ++} ++ ++void detail_board_ddr_info(void) ++{ ++ int i; ++ u64 ddr_size = 0; ++ ++ puts("\nDDR "); ++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) ++ ddr_size += gd->bd->bi_dram[i].size; ++ print_size(ddr_size, ""); ++ print_ddr_info(0); ++} ++ ++#if defined(CONFIG_ARCH_MISC_INIT) ++int arch_misc_init(void) ++{ ++ config_board_mux(); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_FSL_MC_ENET ++extern int fdt_fixup_board_phy(void *fdt); ++ ++void fdt_fixup_board_enet(void *fdt) ++{ ++ int offset; ++ ++ offset = fdt_path_offset(fdt, "/soc/fsl-mc"); ++ ++ if (offset < 0) ++ offset = fdt_path_offset(fdt, "/fsl-mc"); ++ ++ if (offset < 0) { ++ printf("%s: fsl-mc node not found in device tree (error %d)\n", ++ __func__, offset); ++ return; ++ } ++ ++ if (get_mc_boot_status() == 0 && ++ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { ++ fdt_status_okay(fdt, offset); ++ fdt_fixup_board_phy(fdt); ++ } else { ++ fdt_status_fail(fdt, offset); ++ } ++} ++ ++void board_quiesce_devices(void) ++{ ++ fsl_mc_ldpaa_exit(gd->bd); ++} ++#endif ++ ++#ifdef CONFIG_OF_BOARD_SETUP ++ ++int ft_board_setup(void *blob, bd_t *bd) ++{ ++ int i; ++ bool mc_memory_bank = false; ++ ++ u64 *base; ++ u64 *size; ++ u64 mc_memory_base = 0; ++ u64 mc_memory_size = 0; ++ u16 total_memory_banks; ++ ++ ft_cpu_setup(blob, bd); ++ ++ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); ++ ++ if (mc_memory_base != 0) ++ mc_memory_bank = true; ++ ++ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; ++ ++ base = calloc(total_memory_banks, sizeof(u64)); ++ size = calloc(total_memory_banks, sizeof(u64)); ++ ++ /* fixup DT for the three GPP DDR banks */ ++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { ++ base[i] = gd->bd->bi_dram[i].start; ++ size[i] = gd->bd->bi_dram[i].size; ++ } ++ ++#ifdef CONFIG_RESV_RAM ++ /* reduce size if reserved memory is within this bank */ ++ if (gd->arch.resv_ram >= base[0] && ++ gd->arch.resv_ram < base[0] + size[0]) ++ size[0] = gd->arch.resv_ram - base[0]; ++ else if (gd->arch.resv_ram >= base[1] && ++ gd->arch.resv_ram < base[1] + size[1]) ++ size[1] = gd->arch.resv_ram - base[1]; ++ else if (gd->arch.resv_ram >= base[2] && ++ gd->arch.resv_ram < base[2] + size[2]) ++ size[2] = gd->arch.resv_ram - base[2]; ++#endif ++ ++ if (mc_memory_base != 0) { ++ for (i = 0; i <= total_memory_banks; i++) { ++ if (base[i] == 0 && size[i] == 0) { ++ base[i] = mc_memory_base; ++ size[i] = mc_memory_size; ++ break; ++ } ++ } ++ } ++ ++ fdt_fixup_memory_banks(blob, base, size, total_memory_banks); ++ ++#ifdef CONFIG_USB ++ fsl_fdt_fixup_dr_usb(blob, bd); ++#endif ++ ++#ifdef CONFIG_FSL_MC_ENET ++ fdt_fsl_mc_fixup_iommu_map_entry(blob); ++ fdt_fixup_board_enet(blob); ++#endif ++ ++ return 0; ++} ++#endif +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0007-lx2160a-load-dpl-into-0x80001000-instead-of-0x80d000.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0007-lx2160a-load-dpl-into-0x80001000-instead-of-0x80d000.patch new file mode 100644 index 00000000..b5d2d161 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0007-lx2160a-load-dpl-into-0x80001000-instead-of-0x80d000.patch @@ -0,0 +1,47 @@ +From 422b44970b160ee2e8752552a6232e50106a7bd8 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 4 May 2020 23:09:52 +0300 +Subject: [PATCH 07/17] lx2160a: load dpl into 0x80001000 instead of 0x80d00000 + +and enlarge the image size to 0x1000 blocks + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + include/configs/lx2160a_common.h | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h +index c6a6a96ff0..5b9808b2ef 100644 +--- a/include/configs/lx2160a_common.h ++++ b/include/configs/lx2160a_common.h +@@ -293,21 +293,21 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); + + #define SD_BOOTCOMMAND \ + "env exists mcinitcmd && mmcinfo; " \ +- "mmc read 0x80d00000 0x6800 0x800; " \ ++ "mmc read 0x80001000 0x6800 0x1000; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ +- "&& fsl_mc lazyapply dpl 0x80d00000;" \ ++ "&& fsl_mc lazyapply dpl 0x80001000;" \ + "run distro_bootcmd;run sd_bootcmd;" \ + "env exists secureboot && esbc_halt;" + + #define SD2_BOOTCOMMAND \ + "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ +- "mmc read 0x80d00000 0x6800 0x800; " \ ++ "mmc read 0x80001000 0x6800 0x1000; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ +- "&& fsl_mc lazyapply dpl 0x80d00000;" \ ++ "&& fsl_mc lazyapply dpl 0x80001000;" \ + "run distro_bootcmd;run emmc_bootcmd;" \ + "env exists secureboot && esbc_halt;" + +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0008-uboot-add-nvme-commands-and-for-distroboot.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0008-uboot-add-nvme-commands-and-for-distroboot.patch new file mode 100644 index 00000000..6ea81105 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0008-uboot-add-nvme-commands-and-for-distroboot.patch @@ -0,0 +1,41 @@ +From 8fa576d659e4710eae0b62aadd7717846c64746c Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 11 Nov 2019 23:45:31 +0200 +Subject: [PATCH 08/17] uboot - add nvme commands and for distroboot + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + configs/lx2160acex7_tfa_defconfig | 2 ++ + include/configs/lx2160a_common.h | 1 + + 2 files changed, 3 insertions(+) + +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +index d59de7d054..3891d2a7c4 100644 +--- a/configs/lx2160acex7_tfa_defconfig ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -25,6 +25,8 @@ CONFIG_CMD_PCI=y + CONFIG_CMD_SF=y + CONFIG_CMD_USB=y + CONFIG_CMD_CACHE=y ++CONFIG_CMD_NVME=y ++CONFIG_NVME=y + CONFIG_MP=y + CONFIG_OF_CONTROL=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7" +diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h +index 5b9808b2ef..e31738d3a3 100644 +--- a/include/configs/lx2160a_common.h ++++ b/include/configs/lx2160a_common.h +@@ -316,6 +316,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(SCSI, scsi, 0) \ ++ func(NVME, nvme, 0) \ + func(DHCP, dhcp, na) + #include <config_distro_bootcmd.h> + +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch new file mode 100644 index 00000000..e813e423 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch @@ -0,0 +1,33 @@ +From aeefed55fa39f4fc5acb2bd22fdde4dc97924d22 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 13:32:09 +0200 +Subject: [PATCH 09/17] armv8: lx2160acex7: Fix booting from NVMe drives + +Currently NVMe is not initialized so u-boot fails to read kernel from +NVMe drive. This patch modifies default environment so it initializes +NVMe as part of default startup script... + +Credit to Damjan Marion <dmarion@me.com> on fixing that on LSDK-19.09. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + include/configs/lx2160a_common.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h +index e31738d3a3..91e9a2470f 100644 +--- a/include/configs/lx2160a_common.h ++++ b/include/configs/lx2160a_common.h +@@ -261,6 +261,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); + BOOTENV \ + "mcmemsize=0x70000000\0" \ + XSPI_MC_INIT_CMD \ ++ "nvme_need_init=true\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0010-nvme-add-accessor-to-namespace-id-and-eui64.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0010-nvme-add-accessor-to-namespace-id-and-eui64.patch new file mode 100644 index 00000000..d8de8a38 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0010-nvme-add-accessor-to-namespace-id-and-eui64.patch @@ -0,0 +1,90 @@ +From 89dbced60971ec1d01386b0457c20e045cbfe5ad Mon Sep 17 00:00:00 2001 +From: Patrick Wildt <patrick@blueri.se> +Date: Thu, 3 Oct 2019 13:48:47 +0200 +Subject: [PATCH 10/17] nvme: add accessor to namespace id and eui64 + +This adds a function which can be used by e.g. EFI to retrieve +the namespace identifier and EUI64. For that it adds the EUI64 +to its driver internal namespace structure and copies the EUI64 +during namespace identification. + +Upstream-Status: Backport [Solid-Run BSP] + +Signed-off-by: Patrick Wildt <patrick@blueri.se> +Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> +Reviewed-by: Bin Meng <bmeng.cn@gmail.com> +(cherry picked from commit c50b2883dfc1ce355dc37238741ef97cd2c5d000) +Signed-off-by: Olof Johansson <olof@lixom.net> +--- + drivers/nvme/nvme.c | 13 +++++++++++++ + drivers/nvme/nvme.h | 1 + + include/nvme.h | 12 ++++++++++++ + 3 files changed, 26 insertions(+) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 47f101e280..ee6b581d9e 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -621,6 +621,18 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev) + return 0; + } + ++int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64) ++{ ++ struct nvme_ns *ns = dev_get_priv(udev); ++ ++ if (ns_id) ++ *ns_id = ns->ns_id; ++ if (eui64) ++ memcpy(eui64, ns->eui64, sizeof(ns->eui64)); ++ ++ return 0; ++} ++ + int nvme_scan_namespace(void) + { + struct uclass *uc; +@@ -657,6 +669,7 @@ static int nvme_blk_probe(struct udevice *udev) + if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) + return -EIO; + ++ memcpy(&ns->eui64, &id->eui64, sizeof(id->eui64)); + flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK; + ns->flbas = flbas; + ns->lba_shift = id->lbaf[flbas].ds; +diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h +index 922f7abfe8..0e8cb221a7 100644 +--- a/drivers/nvme/nvme.h ++++ b/drivers/nvme/nvme.h +@@ -637,6 +637,7 @@ struct nvme_ns { + struct list_head list; + struct nvme_dev *dev; + unsigned ns_id; ++ u8 eui64[8]; + int devnum; + int lba_shift; + u8 flbas; +diff --git a/include/nvme.h b/include/nvme.h +index 2c3d14d241..2cdf8ce320 100644 +--- a/include/nvme.h ++++ b/include/nvme.h +@@ -78,4 +78,16 @@ int nvme_scan_namespace(void); + */ + int nvme_print_info(struct udevice *udev); + ++/** ++ * nvme_get_namespace_id - return namespace identifier ++ * ++ * This returns the namespace identifier. ++ * ++ * @udev: NVMe controller device ++ * @ns_id: Place where to put the name space identifier ++ * @eui64: Place where to put the IEEE Extended Unique Identifier ++ * @return: 0 on success, -ve on error ++ */ ++int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64); ++ + #endif /* __NVME_H__ */ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0011-nvme-flush-dcache-on-both-r-w-and-the-prp-list.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0011-nvme-flush-dcache-on-both-r-w-and-the-prp-list.patch new file mode 100644 index 00000000..0e0c8d54 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0011-nvme-flush-dcache-on-both-r-w-and-the-prp-list.patch @@ -0,0 +1,51 @@ +From bdc721890d0a68d297959052394da75112080bfe Mon Sep 17 00:00:00 2001 +From: Patrick Wildt <patrick@blueri.se> +Date: Wed, 16 Oct 2019 23:22:50 +0200 +Subject: [PATCH 11/17] nvme: flush dcache on both r/w, and the prp list + +It's possible that the data cache for the buffer still holds data +to be flushed to memory, since the buffer was probably used as stack +before. Thus we need to make sure to flush it also on reads, since +it's possible that the cache is automatically flused to memory after +the NVMe DMA transfer happened, thus overwriting the NVMe transfer's +data. Also add a missing dcache flush for the prp list. + +Upstream-Status: Backport [Solid-Run BSP] + +Signed-off-by: Patrick Wildt <patrick@blueri.se> +Reviewed-by: Bin Meng <bmeng.cn@gmail.com> +(cherry picked from commit 8c403402ca691c967516481b6bc2c879d683a73d) +Signed-off-by: Olof Johansson <olof@lixom.net> +--- + drivers/nvme/nvme.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index ee6b581d9e..53ff6e89aa 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -123,6 +123,9 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + } + *prp2 = (ulong)dev->prp_pool; + ++ flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool + ++ dev->prp_entry_num * sizeof(u64)); ++ + return 0; + } + +@@ -705,9 +708,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); + u64 total_lbas = blkcnt; + +- if (!read) +- flush_dcache_range((unsigned long)buffer, +- (unsigned long)buffer + total_len); ++ flush_dcache_range((unsigned long)buffer, ++ (unsigned long)buffer + total_len); + + c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write; + c.rw.flags = 0; +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0012-nvme-use-page-aligned-buffer-for-identify-command.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0012-nvme-use-page-aligned-buffer-for-identify-command.patch new file mode 100644 index 00000000..c82cd649 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0012-nvme-use-page-aligned-buffer-for-identify-command.patch @@ -0,0 +1,94 @@ +From f6b1bf35c4423eb1f038eca80df4f7d6862f338a Mon Sep 17 00:00:00 2001 +From: Patrick Wildt <patrick@blueri.se> +Date: Wed, 16 Oct 2019 08:42:04 +0200 +Subject: [PATCH 12/17] nvme: use page-aligned buffer for identify command + +Change the stack-allocated buffer for the identification command +to explicitly allocate page-aligned buffers. Even though the spec +seems to allow having admin queue commands on non page-aligned +buffers, it seems to not be possible on my i.MX8MQ board with a +a Silicon Power P34A80. Since all of the NVMe drivers I have seen +always do admin commands on a page-aligned buffer, which does work +on my system, it makes sense for us to do that as well. + +Upstream-Status: Backport [Solid-Run BSP] + +Signed-off-by: Patrick Wildt <patrick@blueri.se> +Reviewed-by: Bin Meng <bmeng.cn@gmail.com> +(cherry picked from commit 2f83481dff9c4f253a6ac341911d78d4984ca07b) +Signed-off-by: Olof Johansson <olof@lixom.net> +--- + drivers/nvme/nvme.c | 24 ++++++++++++++++++------ + 1 file changed, 18 insertions(+), 6 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 53ff6e89aa..f915817aaa 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -583,14 +583,19 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) + + static int nvme_get_info_from_identify(struct nvme_dev *dev) + { +- ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl)); +- struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf; ++ struct nvme_id_ctrl *ctrl; + int ret; + int shift = NVME_CAP_MPSMIN(dev->cap) + 12; + ++ ctrl = memalign(dev->page_size, sizeof(struct nvme_id_ctrl)); ++ if (!ctrl) ++ return -ENOMEM; ++ + ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl); +- if (ret) ++ if (ret) { ++ free(ctrl); + return -EIO; ++ } + + dev->nn = le32_to_cpu(ctrl->nn); + dev->vwc = ctrl->vwc; +@@ -621,6 +626,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev) + dev->max_transfer_shift = 20; + } + ++ free(ctrl); + return 0; + } + +@@ -661,16 +667,21 @@ static int nvme_blk_probe(struct udevice *udev) + struct blk_desc *desc = dev_get_uclass_platdata(udev); + struct nvme_ns *ns = dev_get_priv(udev); + u8 flbas; +- ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns)); +- struct nvme_id_ns *id = (struct nvme_id_ns *)buf; + struct pci_child_platdata *pplat; ++ struct nvme_id_ns *id; ++ ++ id = memalign(ndev->page_size, sizeof(struct nvme_id_ns)); ++ if (!id) ++ return -ENOMEM; + + memset(ns, 0, sizeof(*ns)); + ns->dev = ndev; + /* extract the namespace id from the block device name */ + ns->ns_id = trailing_strtol(udev->name) + 1; +- if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) ++ if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) { ++ free(id); + return -EIO; ++ } + + memcpy(&ns->eui64, &id->eui64, sizeof(id->eui64)); + flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK; +@@ -689,6 +700,7 @@ static int nvme_blk_probe(struct udevice *udev) + memcpy(desc->product, ndev->serial, sizeof(ndev->serial)); + memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev)); + ++ free(id); + return 0; + } + +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0013-lx2160a-cex7-move-from-lsdk-19.06-to-lsdk-19.09.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0013-lx2160a-cex7-move-from-lsdk-19.06-to-lsdk-19.09.patch new file mode 100644 index 00000000..0ccb2eb9 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0013-lx2160a-cex7-move-from-lsdk-19.06-to-lsdk-19.09.patch @@ -0,0 +1,923 @@ +From 4672d506d0abfba7890b2719b7b53f3694b88d06 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 3 Feb 2020 14:26:55 +0200 +Subject: [PATCH 13/17] lx2160a-cex7 : move from lsdk-19.06 to lsdk-19.09 + +Following is a list of changes - +1. I2C moved to DM model +2. removed emc2301 support +3. synchronized vid.c with NXP's driver. But it is still not functional +in u-boot +4. Added eMMC to distroboot target list + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + arch/arm/dts/fsl-lx2160a-cex7.dts | 14 + + board/solidrun/common/Makefile | 1 - + board/solidrun/common/emc2301.c | 31 -- + board/solidrun/common/vid.c | 638 +++++++++++++++++++++++++++++- + board/solidrun/lx2160a/lx2160a.c | 8 + + configs/lx2160acex7_tfa_defconfig | 8 +- + 6 files changed, 665 insertions(+), 35 deletions(-) + delete mode 100644 board/solidrun/common/emc2301.c + +diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts +index 4fbcaafb0e..4ca67df25a 100644 +--- a/arch/arm/dts/fsl-lx2160a-cex7.dts ++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts +@@ -46,6 +46,20 @@ + status = "okay"; + }; + ++&i2c0 { ++ status = "okay"; ++ u-boot,dm-pre-reloc; ++}; ++ ++&i2c4 { ++ status = "okay"; ++ ++ rtc@51 { ++ compatible = "pcf2127-rtc"; ++ reg = <0x51>; ++ }; ++}; ++ + &sata0 { + status = "okay"; + }; +diff --git a/board/solidrun/common/Makefile b/board/solidrun/common/Makefile +index 454a18e2f9..c335c658d4 100644 +--- a/board/solidrun/common/Makefile ++++ b/board/solidrun/common/Makefile +@@ -16,7 +16,6 @@ ifdef MINIMAL + obj- := __dummy__.o + else + obj-$(CONFIG_VID) += vid.o +-obj-$(CONFIG_EMC2301) += emc2301.o + ifdef CONFIG_SECURE_BOOT + obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o + endif +diff --git a/board/solidrun/common/emc2301.c b/board/solidrun/common/emc2301.c +deleted file mode 100644 +index a4780dbfcc..0000000000 +--- a/board/solidrun/common/emc2301.c ++++ /dev/null +@@ -1,31 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2019 SolidRun ltd. Based on code from NXP LX2160A RDB +- * +- * SPDX-License-Identifier: GPL-2.0+ +- */ +- +-#include <common.h> +-#include <command.h> +-#include <i2c.h> +-#include <asm/io.h> +- +-#include "emc2301.h" +- +-DECLARE_GLOBAL_DATA_PTR; +- +-void set_fan_speed(u8 data) +-{ +- if (i2c_write(I2C_EMC2301_ADDR, I2C_EMC2301_FAN, 1, &data, 1) != 0) { +- puts("Error: failed to change fan speed\n"); +- } +-} +- +-void emc2301_init(void) +-{ +- u8 data; +- +- data = I2C_EMC2301_CMD; +- if (i2c_write(I2C_EMC2301_ADDR, I2C_EMC2301_CONF, 1, &data, 1) != 0) +- puts("Error: failed to configure EMC2301\n"); +-} +diff --git a/board/solidrun/common/vid.c b/board/solidrun/common/vid.c +index cc81e80c37..c7a626fd4f 100644 +--- a/board/solidrun/common/vid.c ++++ b/board/solidrun/common/vid.c +@@ -1,8 +1,9 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2014 Freescale Semiconductor, Inc. +- * Copyright 2018 NXP ++ * Copyright 2019 NXP + */ ++ + #include <common.h> + #include <command.h> + #include <i2c.h> +@@ -38,6 +39,52 @@ int __weak board_adjust_vdd(int vdd) + return 0; + } + ++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ ++ defined(CONFIG_VOL_MONITOR_IR36021_READ) ++/* ++ * Get the i2c address configuration for the IR regulator chip ++ * ++ * There are some variance in the RDB HW regarding the I2C address configuration ++ * for the IR regulator chip, which is likely a problem of external resistor ++ * accuracy. So we just check each address in a hopefully non-intrusive mode ++ * and use the first one that seems to work ++ * ++ * The IR chip can show up under the following addresses: ++ * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) ++ * 0x09 (Verified on T1040RDB-PA) ++ * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB) ++ */ ++static int find_ir_chip_on_i2c(void) ++{ ++ int i2caddress; ++ int ret; ++ u8 byte; ++ int i; ++ const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; ++#ifdef CONFIG_DM_I2C ++ struct udevice *dev; ++#endif ++ ++ /* Check all the address */ ++ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { ++ i2caddress = ir_i2c_addr[i]; ++#ifndef CONFIG_DM_I2C ++ ret = i2c_read(i2caddress, ++ IR36021_MFR_ID_OFFSET, 1, (void *)&byte, ++ sizeof(byte)); ++#else ++ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET, ++ (void *)&byte, sizeof(byte)); ++#endif ++ if ((ret >= 0) && (byte == IR36021_MFR_ID)) ++ return i2caddress; ++ } ++ return -1; ++} ++#endif ++ + /* Maximum loop count waiting for new voltage to take effect */ + #define MAX_LOOP_WAIT_NEW_VOL 100 + /* Maximum loop count waiting for the voltage to be stable */ +@@ -60,23 +107,135 @@ int __weak board_adjust_vdd(int vdd) + #define ADC_MIN_ACCURACY 4 + #endif + ++#ifdef CONFIG_VOL_MONITOR_INA220 ++static int read_voltage_from_INA220(int i2caddress) ++{ ++ int i, ret, voltage_read = 0; ++ u16 vol_mon; ++ u8 buf[2]; ++#ifdef CONFIG_DM_I2C ++ struct udevice *dev; ++#endif ++ ++ for (i = 0; i < NUM_READINGS; i++) { ++#ifndef CONFIG_DM_I2C ++ ret = i2c_read(I2C_VOL_MONITOR_ADDR, ++ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, ++ (void *)&buf, 2); ++#else ++ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, ++ (void *)&buf, 2); ++#endif ++ if (ret) { ++ printf("VID: failed to read core voltage\n"); ++ return ret; ++ } ++ vol_mon = (buf[0] << 8) | buf[1]; ++ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { ++ printf("VID: Core voltage sensor error\n"); ++ return -1; ++ } ++ debug("VID: bus voltage reads 0x%04x\n", vol_mon); ++ /* LSB = 4mv */ ++ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; ++ udelay(WAIT_FOR_ADC); ++ } ++ /* calculate the average */ ++ voltage_read /= NUM_READINGS; ++ ++ return voltage_read; ++} ++#endif ++ ++/* read voltage from IR */ ++#ifdef CONFIG_VOL_MONITOR_IR36021_READ ++static int read_voltage_from_IR(int i2caddress) ++{ ++ int i, ret, voltage_read = 0; ++ u16 vol_mon; ++ u8 buf; ++#ifdef CONFIG_DM_I2C ++ struct udevice *dev; ++#endif ++ ++ for (i = 0; i < NUM_READINGS; i++) { ++#ifndef CONFIG_DM_I2C ++ ret = i2c_read(i2caddress, ++ IR36021_LOOP1_VOUT_OFFSET, ++ 1, (void *)&buf, 1); ++#else ++ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET, ++ (void *)&buf, 1); ++#endif ++ if (ret) { ++ printf("VID: failed to read vcpu\n"); ++ return ret; ++ } ++ vol_mon = buf; ++ if (!vol_mon) { ++ printf("VID: Core voltage sensor error\n"); ++ return -1; ++ } ++ debug("VID: bus voltage reads 0x%02x\n", vol_mon); ++ /* Resolution is 1/128V. We scale up here to get 1/128mV ++ * and divide at the end ++ */ ++ voltage_read += vol_mon * 1000; ++ udelay(WAIT_FOR_ADC); ++ } ++ /* Scale down to the real mV as IR resolution is 1/128V, rounding up */ ++ voltage_read = DIV_ROUND_UP(voltage_read, 128); ++ ++ /* calculate the average */ ++ voltage_read /= NUM_READINGS; ++ ++ /* Compensate for a board specific voltage drop between regulator and ++ * SoC before converting into an IR VID value ++ */ ++ voltage_read -= board_vdd_drop_compensation(); ++ ++ return voltage_read; ++} ++#endif ++ ++#ifdef CONFIG_VOL_MONITOR_LTC3882_READ + /* read the current value of the LTC Regulator Voltage */ + static int read_voltage_from_LTC(int i2caddress) + { + int ret, vcode = 0; + u8 chan = PWM_CHANNEL0; + ++#ifndef CONFIG_DM_I2C + /* select the PAGE 0 using PMBus commands PAGE for VDD*/ + ret = i2c_write(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_PAGE, 1, &chan, 1); ++#else ++ struct udevice *dev; ++ ++ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1); ++#endif + if (ret) { + printf("VID: failed to select VDD Page 0\n"); + return ret; + } + ++#ifndef CONFIG_DM_I2C + /*read the output voltage using PMBus command READ_VOUT*/ + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); ++#else ++ ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); ++ if (ret) { ++ printf("VID: failed to read the volatge\n"); ++ return ret; ++ } ++#endif + if (ret) { + printf("VID: failed to read the volatge\n"); + return ret; +@@ -87,14 +246,131 @@ static int read_voltage_from_LTC(int i2caddress) + + return vcode; + } ++#endif + + static int read_voltage(int i2caddress) + { + int voltage_read; ++#ifdef CONFIG_VOL_MONITOR_INA220 ++ voltage_read = read_voltage_from_INA220(i2caddress); ++#elif defined CONFIG_VOL_MONITOR_IR36021_READ ++ voltage_read = read_voltage_from_IR(i2caddress); ++#elif defined CONFIG_VOL_MONITOR_LTC3882_READ + voltage_read = read_voltage_from_LTC(i2caddress); ++#else ++ return -1; ++#endif + return voltage_read; + } + ++#ifdef CONFIG_VOL_MONITOR_IR36021_SET ++/* ++ * We need to calculate how long before the voltage stops to drop ++ * or increase. It returns with the loop count. Each loop takes ++ * several readings (WAIT_FOR_ADC) ++ */ ++static int wait_for_new_voltage(int vdd, int i2caddress) ++{ ++ int timeout, vdd_current; ++ ++ vdd_current = read_voltage(i2caddress); ++ /* wait until voltage starts to reach the target. Voltage slew ++ * rates by typical regulators will always lead to stable readings ++ * within each fairly long ADC interval in comparison to the ++ * intended voltage delta change until the target voltage is ++ * reached. The fairly small voltage delta change to any target ++ * VID voltage also means that this function will always complete ++ * within few iterations. If the timeout was ever reached, it would ++ * point to a serious failure in the regulator system. ++ */ ++ for (timeout = 0; ++ abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) && ++ timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) { ++ vdd_current = read_voltage(i2caddress); ++ } ++ if (timeout >= MAX_LOOP_WAIT_NEW_VOL) { ++ printf("VID: Voltage adjustment timeout\n"); ++ return -1; ++ } ++ return timeout; ++} ++ ++/* ++ * this function keeps reading the voltage until it is stable or until the ++ * timeout expires ++ */ ++static int wait_for_voltage_stable(int i2caddress) ++{ ++ int timeout, vdd_current, vdd; ++ ++ vdd = read_voltage(i2caddress); ++ udelay(NUM_READINGS * WAIT_FOR_ADC); ++ ++ /* wait until voltage is stable */ ++ vdd_current = read_voltage(i2caddress); ++ /* The maximum timeout is ++ * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC ++ */ ++ for (timeout = MAX_LOOP_WAIT_VOL_STABLE; ++ abs(vdd - vdd_current) > ADC_MIN_ACCURACY && ++ timeout > 0; timeout--) { ++ vdd = vdd_current; ++ udelay(NUM_READINGS * WAIT_FOR_ADC); ++ vdd_current = read_voltage(i2caddress); ++ } ++ if (timeout == 0) ++ return -1; ++ return vdd_current; ++} ++ ++/* Set the voltage to the IR chip */ ++static int set_voltage_to_IR(int i2caddress, int vdd) ++{ ++ int wait, vdd_last; ++ int ret; ++ u8 vid; ++ ++ /* Compensate for a board specific voltage drop between regulator and ++ * SoC before converting into an IR VID value ++ */ ++ vdd += board_vdd_drop_compensation(); ++#ifdef CONFIG_FSL_LSCH2 ++ vid = DIV_ROUND_UP(vdd - 265, 5); ++#else ++ vid = DIV_ROUND_UP(vdd - 245, 5); ++#endif ++ ++#ifndef CONFIG_DM_I2C ++ ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, ++ 1, (void *)&vid, sizeof(vid)); ++#else ++ struct udevice *dev; ++ ++ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, ++ (void *)&vid, sizeof(vid)); ++ ++#endif ++ if (ret) { ++ printf("VID: failed to write VID\n"); ++ return -1; ++ } ++ wait = wait_for_new_voltage(vdd, i2caddress); ++ if (wait < 0) ++ return -1; ++ debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); ++ ++ vdd_last = wait_for_voltage_stable(i2caddress); ++ if (vdd_last < 0) ++ return -1; ++ debug("VID: Current voltage is %d mV\n", vdd_last); ++ return vdd_last; ++} ++ ++#endif ++ ++#ifdef CONFIG_VOL_MONITOR_LTC3882_SET + /* this function sets the VDD and returns the value set */ + static int set_voltage_to_LTC(int i2caddress, int vdd) + { +@@ -111,8 +387,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) + vdd & 0xFF, (vdd & 0xFF00) >> 8}; + + /* Write the desired voltage code to the regulator */ ++#ifndef CONFIG_DM_I2C + ret = i2c_write(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); ++#else ++ struct udevice *dev; ++ ++ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, ++ (void *)&buff, 5); ++#endif + if (ret) { + printf("VID: I2C failed to write to the volatge regulator\n"); + return -1; +@@ -131,25 +416,39 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) + + return vdd_last; + } ++#endif + + static int set_voltage(int i2caddress, int vdd) + { + int vdd_last = -1; + ++#ifdef CONFIG_VOL_MONITOR_IR36021_SET ++ vdd_last = set_voltage_to_IR(i2caddress, vdd); ++#elif defined CONFIG_VOL_MONITOR_LTC3882_SET + vdd_last = set_voltage_to_LTC(i2caddress, vdd); ++#else ++ #error Specific voltage monitor must be defined ++#endif + return vdd_last; + } + ++#ifdef CONFIG_FSL_LSCH3 + int adjust_vdd(ulong vdd_override) + { + int re_enable = disable_interrupts(); + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 fusesr; ++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ ++ defined(CONFIG_VOL_MONITOR_IR36021_READ) ++ u8 vid, buf; ++#else + u8 vid; ++#endif + int vdd_target, vdd_current, vdd_last; + int ret, i2caddress; + unsigned long vdd_string_override; + char *vdd_string; ++#ifdef CONFIG_ARCH_LX2160A + static const u16 vdd[32] = { + 8250, + 7875, +@@ -184,16 +483,129 @@ int adjust_vdd(ulong vdd_override) + 0, /* reserved */ + 0, /* reserved */ + }; ++#else ++#ifdef CONFIG_ARCH_LS1088A ++ static const uint16_t vdd[32] = { ++ 10250, ++ 9875, ++ 9750, ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 9000, ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 10000, /* 1.0000V */ ++ 10125, ++ 10250, ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ }; ++ ++#else ++ static const uint16_t vdd[32] = { ++ 10500, ++ 0, /* reserved */ ++ 9750, ++ 0, /* reserved */ ++ 9500, ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 9000, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 10000, /* 1.0000V */ ++ 0, /* reserved */ ++ 10250, ++ 0, /* reserved */ ++ 10500, ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ 0, /* reserved */ ++ }; ++#endif ++#endif + struct vdd_drive { + u8 vid; + unsigned voltage; + }; ++ + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2C failed to switch channel\n"); + ret = -1; + goto exit; + } ++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ ++ defined(CONFIG_VOL_MONITOR_IR36021_READ) ++ ret = find_ir_chip_on_i2c(); ++ if (ret < 0) { ++ printf("VID: Could not find voltage regulator on I2C.\n"); ++ ret = -1; ++ goto exit; ++ } else { ++ i2caddress = ret; ++ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); ++ } ++ ++ /* check IR chip work on Intel mode*/ ++#ifndef CONFIG_DM_I2C ++ ret = i2c_read(i2caddress, ++ IR36021_INTEL_MODE_OOFSET, ++ 1, (void *)&buf, 1); ++#else ++ struct udevice *dev; ++ ++ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, ++ (void *)&buf, 1); ++#endif ++ if (ret) { ++ printf("VID: failed to read IR chip mode.\n"); ++ ret = -1; ++ goto exit; ++ } ++ ++ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { ++ printf("VID: IR Chip is not used in Intel mode.\n"); ++ ret = -1; ++ goto exit; ++ } ++#endif ++ + /* get the voltage ID from fuse status register */ + fusesr = in_le32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & +@@ -203,7 +615,6 @@ int adjust_vdd(ulong vdd_override) + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } + vdd_target = vdd[vid]; +- printf ("vid FUSE index %d (vdd_target = %d)\n",vid,vdd_target); + + /* check override variable for overriding VDD */ + vdd_string = env_get(CONFIG_VID_FLS_ENV); +@@ -246,8 +657,28 @@ int adjust_vdd(ulong vdd_override) + vdd_current = vdd_last; + debug("VID: Core voltage is currently at %d mV\n", vdd_last); + ++#ifdef CONFIG_VOL_MONITOR_LTC3882_SET + /* Set the target voltage */ + vdd_last = vdd_current = set_voltage(i2caddress, vdd_target); ++#else ++ /* ++ * Adjust voltage to at or one step above target. ++ * As measurements are less precise than setting the values ++ * we may run through dummy steps that cancel each other ++ * when stepping up and then down. ++ */ ++ while (vdd_last > 0 && ++ vdd_last < vdd_target) { ++ vdd_current += IR_VDD_STEP_UP; ++ vdd_last = set_voltage(i2caddress, vdd_current); ++ } ++ while (vdd_last > 0 && ++ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { ++ vdd_current -= IR_VDD_STEP_DOWN; ++ vdd_last = set_voltage(i2caddress, vdd_current); ++ } ++ ++#endif + if (board_adjust_vdd(vdd_target) < 0) { + ret = -1; + goto exit; +@@ -264,6 +695,197 @@ exit: + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + return ret; + } ++#else /* !CONFIG_FSL_LSCH3 */ ++int adjust_vdd(ulong vdd_override) ++{ ++ int re_enable = disable_interrupts(); ++#if defined(CONFIG_FSL_LSCH2) ++ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); ++#else ++ ccsr_gur_t __iomem *gur = ++ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ++#endif ++ u32 fusesr; ++ u8 vid, buf; ++ int vdd_target, vdd_current, vdd_last; ++ int ret, i2caddress; ++ unsigned long vdd_string_override; ++ char *vdd_string; ++ static const uint16_t vdd[32] = { ++ 0, /* unused */ ++ 9875, /* 0.9875V */ ++ 9750, ++ 9625, ++ 9500, ++ 9375, ++ 9250, ++ 9125, ++ 9000, ++ 8875, ++ 8750, ++ 8625, ++ 8500, ++ 8375, ++ 8250, ++ 8125, ++ 10000, /* 1.0000V */ ++ 10125, ++ 10250, ++ 10375, ++ 10500, ++ 10625, ++ 10750, ++ 10875, ++ 11000, ++ 0, /* reserved */ ++ }; ++ struct vdd_drive { ++ u8 vid; ++ unsigned voltage; ++ }; ++ ++ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); ++ if (ret) { ++ debug("VID: I2C failed to switch channel\n"); ++ ret = -1; ++ goto exit; ++ } ++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ ++ defined(CONFIG_VOL_MONITOR_IR36021_READ) ++ ret = find_ir_chip_on_i2c(); ++ if (ret < 0) { ++ printf("VID: Could not find voltage regulator on I2C.\n"); ++ ret = -1; ++ goto exit; ++ } else { ++ i2caddress = ret; ++ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); ++ } ++ ++ /* check IR chip work on Intel mode*/ ++#ifndef CONFIG_DM_I2C ++ ret = i2c_read(i2caddress, ++ IR36021_INTEL_MODE_OOFSET, ++ 1, (void *)&buf, 1); ++#else ++ struct udevice *dev; ++ ++ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, ++ (void *)&buf, 1); ++#endif ++ if (ret) { ++ printf("VID: failed to read IR chip mode.\n"); ++ ret = -1; ++ goto exit; ++ } ++ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { ++ printf("VID: IR Chip is not used in Intel mode.\n"); ++ ret = -1; ++ goto exit; ++ } ++#endif ++ ++ /* get the voltage ID from fuse status register */ ++ fusesr = in_be32(&gur->dcfg_fusesr); ++ /* ++ * VID is used according to the table below ++ * --------------------------------------- ++ * | DA_V | ++ * |-------------------------------------| ++ * | 5b00000 | 5b00001-5b11110 | 5b11111 | ++ * ---------------+---------+-----------------+---------| ++ * | D | 5b00000 | NO VID | VID = DA_V | NO VID | ++ * | A |----------+---------+-----------------+---------| ++ * | _ | 5b00001 |VID = | VID = |VID = | ++ * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| ++ * | _ | 5b11110 | | | | ++ * | A |----------+---------+-----------------+---------| ++ * | L | 5b11111 | No VID | VID = DA_V | NO VID | ++ * | T | | | | | ++ * ------------------------------------------------------ ++ */ ++#ifdef CONFIG_FSL_LSCH2 ++ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & ++ FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; ++ if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { ++ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & ++ FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; ++ } ++#else ++ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & ++ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; ++ if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { ++ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & ++ FSL_CORENET_DCFG_FUSESR_VID_MASK; ++ } ++#endif ++ vdd_target = vdd[vid]; ++ ++ /* check override variable for overriding VDD */ ++ vdd_string = env_get(CONFIG_VID_FLS_ENV); ++ if (vdd_override == 0 && vdd_string && ++ !strict_strtoul(vdd_string, 10, &vdd_string_override)) ++ vdd_override = vdd_string_override; ++ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { ++ vdd_target = vdd_override * 10; /* convert to 1/10 mV */ ++ debug("VDD override is %lu\n", vdd_override); ++ } else if (vdd_override != 0) { ++ printf("Invalid value.\n"); ++ } ++ if (vdd_target == 0) { ++ debug("VID: VID not used\n"); ++ ret = 0; ++ goto exit; ++ } else { ++ /* divide and round up by 10 to get a value in mV */ ++ vdd_target = DIV_ROUND_UP(vdd_target, 10); ++ debug("VID: vid = %d mV\n", vdd_target); ++ } ++ ++ /* ++ * Read voltage monitor to check real voltage. ++ */ ++ vdd_last = read_voltage(i2caddress); ++ if (vdd_last < 0) { ++ printf("VID: Couldn't read sensor abort VID adjustment\n"); ++ ret = -1; ++ goto exit; ++ } ++ vdd_current = vdd_last; ++ debug("VID: Core voltage is currently at %d mV\n", vdd_last); ++ /* ++ * Adjust voltage to at or one step above target. ++ * As measurements are less precise than setting the values ++ * we may run through dummy steps that cancel each other ++ * when stepping up and then down. ++ */ ++ while (vdd_last > 0 && ++ vdd_last < vdd_target) { ++ vdd_current += IR_VDD_STEP_UP; ++ vdd_last = set_voltage(i2caddress, vdd_current); ++ } ++ while (vdd_last > 0 && ++ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { ++ vdd_current -= IR_VDD_STEP_DOWN; ++ vdd_last = set_voltage(i2caddress, vdd_current); ++ } ++ ++ if (vdd_last > 0) ++ printf("VID: Core voltage after adjustment is at %d mV\n", ++ vdd_last); ++ else ++ ret = -1; ++exit: ++ if (re_enable) ++ enable_interrupts(); ++ ++ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); ++ ++ return ret; ++} ++#endif + + static int print_vdd(void) + { +@@ -274,6 +896,18 @@ static int print_vdd(void) + debug("VID : I2c failed to switch channel\n"); + return -1; + } ++#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ ++ defined(CONFIG_VOL_MONITOR_IR36021_READ) ++ ret = find_ir_chip_on_i2c(); ++ if (ret < 0) { ++ printf("VID: Could not find voltage regulator on I2C.\n"); ++ goto exit; ++ } else { ++ i2caddress = ret; ++ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); ++ } ++#endif ++ + /* + * Read voltage monitor to check real voltage. + */ +diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c +index b0d9f1012e..3713e91351 100644 +--- a/board/solidrun/lx2160a/lx2160a.c ++++ b/board/solidrun/lx2160a/lx2160a.c +@@ -62,7 +62,15 @@ int select_i2c_ch_pca9547(u8 ch) + { + int ret; + ++#ifndef CONFIG_DM_I2C + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); ++#else ++ struct udevice *dev; ++ ++ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_write(dev, 0, &ch, 1); ++#endif + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +index 3891d2a7c4..89a47adb23 100644 +--- a/configs/lx2160acex7_tfa_defconfig ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_TARGET_LX2160ACEX7=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SYS_MALLOC_F_LEN=0x6000 +-CONFIG_EMC2301=y + CONFIG_TFABOOT=y + CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y + CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +@@ -73,3 +72,10 @@ CONFIG_DM_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y + CONFIG_EFI_LOADER_BOUNCE_BUFFER=y ++CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_I2C_DEFAULT_BUS_NUMBER=0 ++CONFIG_DM_RTC=y ++CONFIG_DM_GPIO=y ++CONFIG_CMD_DATE=y ++CONFIG_RTC_PCF2127=y +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0014-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0014-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch new file mode 100644 index 00000000..4505f2cf --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0014-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch @@ -0,0 +1,128 @@ +From 5d45e2ab0e00cc809c11a3d0a412022f25639c58 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 12:53:48 +0200 +Subject: [PATCH 14/17] lx2160acex7: pcie fixup and boot from eMMC print + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + board/solidrun/lx2160a/lx2160a.c | 66 +++++++++++++++++++++++++++++++ + configs/lx2160acex7_tfa_defconfig | 3 +- + 2 files changed, 68 insertions(+), 1 deletion(-) + +diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c +index 3713e91351..b7211a2d5c 100644 +--- a/board/solidrun/lx2160a/lx2160a.c ++++ b/board/solidrun/lx2160a/lx2160a.c +@@ -20,6 +20,8 @@ + #include <efi_loader.h> + #include <asm/arch/mmu.h> + #include <hwconfig.h> ++#include <asm/arch/clock.h> ++#include <asm/arch/config.h> + #include <asm/arch/fsl_serdes.h> + #include <asm/arch/soc.h> + #include "../../freescale/common/vid.h" +@@ -106,6 +108,66 @@ int board_early_init_f(void) + #ifdef CONFIG_OF_BOARD_FIXUP + int board_fix_fdt(void *fdt) + { ++ char *reg_name, *old_str, *new_str; ++ const char *reg_names; ++ int names_len, old_str_len, new_str_len, remaining_str_len; ++ struct str_map { ++ char *old_str; ++ char *new_str; ++ } reg_names_map[] = { ++ { "ccsr", "dbi" }, ++ { "pf_ctrl", "ctrl" } ++ }; ++ int off = -1, i; ++ ++ if (IS_SVR_REV(get_svr(), 1, 0)) ++ return 0; ++ ++ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie"); ++ while (off != -FDT_ERR_NOTFOUND) { ++ fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", ++ strlen("fsl,ls-pcie") + 1); ++ ++ reg_names = fdt_getprop(fdt, off, "reg-names", &names_len); ++ if (!reg_names) ++ continue; ++ ++ reg_name = (char *)reg_names; ++ remaining_str_len = names_len - (reg_name - reg_names); ++ i = 0; ++ while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) { ++ old_str = reg_names_map[i].old_str; ++ new_str = reg_names_map[i].new_str; ++ old_str_len = strlen(old_str); ++ new_str_len = strlen(new_str); ++ if (memcmp(reg_name, old_str, old_str_len) == 0) { ++ /* first only leave required bytes for new_str ++ * and copy rest of the string after it ++ */ ++ memcpy(reg_name + new_str_len, ++ reg_name + old_str_len, ++ remaining_str_len - old_str_len); ++ /* Now copy new_str */ ++ memcpy(reg_name, new_str, new_str_len); ++ names_len -= old_str_len; ++ names_len += new_str_len; ++ i++; ++ } ++ ++ reg_name = memchr(reg_name, '\0', remaining_str_len); ++ if (!reg_name) ++ break; ++ ++ reg_name += 1; ++ ++ remaining_str_len = names_len - (reg_name - reg_names); ++ } ++ ++ fdt_setprop(fdt, off, "reg-names", reg_names, names_len); ++ off = fdt_node_offset_by_compatible(fdt, off, ++ "fsl,lx2160a-pcie"); ++ } ++ + return 0; + } + #endif +@@ -135,6 +197,10 @@ int checkboard(void) + + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); ++ } else if (src == BOOT_SOURCE_SD_MMC2) { ++ puts("eMMC\n"); ++ } else { ++ puts("FlexSPI DEV#0\n"); + } + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +index 89a47adb23..2a3441d263 100644 +--- a/configs/lx2160acex7_tfa_defconfig ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -2,6 +2,7 @@ CONFIG_ARM=y + CONFIG_TARGET_LX2160ACEX7=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SYS_MALLOC_F_LEN=0x6000 ++CONFIG_FSPI_AHB_EN_4BYTE=y + CONFIG_TFABOOT=y + CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y + CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +@@ -58,7 +59,7 @@ CONFIG_PCI=y + CONFIG_DM_PCI=y + CONFIG_DM_PCI_COMPAT=y + CONFIG_PCIE_LAYERSCAPE_GEN4=y +-CONFIG_PHY_ATHEROS=y ++CONFIG_PCIE_LAYERSCAPE=y + CONFIG_E1000=y + CONFIG_DM_SCSI=y + CONFIG_DM_SERIAL=y +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0015-lx2160a-cex7-set-mmc-dev-to-0-when-attempting-sd_boo.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0015-lx2160a-cex7-set-mmc-dev-to-0-when-attempting-sd_boo.patch new file mode 100644 index 00000000..ce8dec3f --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0015-lx2160a-cex7-set-mmc-dev-to-0-when-attempting-sd_boo.patch @@ -0,0 +1,32 @@ +From 47923a2f4cf159963d20acd1744619b44c9d5b02 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 15:13:11 +0200 +Subject: [PATCH 15/17] lx2160a-cex7: set mmc dev to 0 when attempting + sd_bootcmd + +When attempting sd_bootcmd which is the fallback of failed distroboot +then set mmc dev to 0; since distroboot already set that variable to 1. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + include/configs/lx2160acex7.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h +index 478cd8242f..7116e038a1 100644 +--- a/include/configs/lx2160acex7.h ++++ b/include/configs/lx2160acex7.h +@@ -73,7 +73,7 @@ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ +- "mmcinfo; mmc read $load_addr " \ ++ "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0016-lx2160acex7-Misc-fixes-to-support-LSDK-20.04.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0016-lx2160acex7-Misc-fixes-to-support-LSDK-20.04.patch new file mode 100644 index 00000000..83e2139c --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0016-lx2160acex7-Misc-fixes-to-support-LSDK-20.04.patch @@ -0,0 +1,127 @@ +From eacde91ef9d8b05ad4df8b6755dd3726e40fb75c Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 4 May 2020 22:52:02 +0300 +Subject: [PATCH 16/17] lx2160acex7: Misc fixes to support LSDK-20.04 + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + arch/arm/Kconfig | 1 + + board/solidrun/lx2160a/lx2160a.c | 4 +++- + configs/lx2160acex7_tfa_defconfig | 24 ++++++++++++------------ + 3 files changed, 16 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 8615e1673f..c78e17a0ed 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1195,6 +1195,7 @@ config TARGET_LX2160ACEX7 + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY ++ select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT + help + Support for SolidRun LX2160A based com express type 7 module and +diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c +index b7211a2d5c..975431fd53 100644 +--- a/board/solidrun/lx2160a/lx2160a.c ++++ b/board/solidrun/lx2160a/lx2160a.c +@@ -16,7 +16,7 @@ + #include <fdt_support.h> + #include <linux/libfdt.h> + #include <fsl-mc/fsl_mc.h> +-#include <environment.h> ++#include <env_internal.h> + #include <efi_loader.h> + #include <asm/arch/mmu.h> + #include <hwconfig.h> +@@ -26,6 +26,8 @@ + #include <asm/arch/soc.h> + #include "../../freescale/common/vid.h" + #include <fsl_immap.h> ++#include <asm/arch-fsl-layerscape/fsl_icid.h> ++#include <asm/gic-v3.h> + + #ifdef CONFIG_EMC2301 + #include "../common/emc2301.h" +diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig +index 2a3441d263..d2e62a6e91 100644 +--- a/configs/lx2160acex7_tfa_defconfig ++++ b/configs/lx2160acex7_tfa_defconfig +@@ -1,16 +1,15 @@ + CONFIG_ARM=y + CONFIG_TARGET_LX2160ACEX7=y ++CONFIG_TFABOOT=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SYS_MALLOC_F_LEN=0x6000 + CONFIG_FSPI_AHB_EN_4BYTE=y +-CONFIG_TFABOOT=y ++CONFIG_NR_DRAM_BANKS=3 + CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y + CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y + CONFIG_AHCI=y +-CONFIG_NR_DRAM_BANKS=3 + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_OF_BOARD_FIXUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -29,6 +28,7 @@ CONFIG_CMD_NVME=y + CONFIG_NVME=y + CONFIG_MP=y + CONFIG_OF_CONTROL=y ++CONFIG_OF_BOARD_FIXUP=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7" + CONFIG_ENV_IS_IN_MMC=y + CONFIG_ENV_IS_IN_SPI_FLASH=y +@@ -36,6 +36,10 @@ CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_DM_MMC=y + CONFIG_FSL_ESDHC=y + CONFIG_DM_SPI_FLASH=y +@@ -55,28 +59,24 @@ CONFIG_CMD_MII=y + CONFIG_CMD_DHCP=y + CONFIG_CMD_FAT=y + CONFIG_CMD_EXT2=y ++CONFIG_E1000=y + CONFIG_PCI=y + CONFIG_DM_PCI=y + CONFIG_DM_PCI_COMPAT=y + CONFIG_PCIE_LAYERSCAPE_GEN4=y + CONFIG_PCIE_LAYERSCAPE=y +-CONFIG_E1000=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF2127=y ++ + CONFIG_DM_SCSI=y + CONFIG_DM_SERIAL=y +-CONFIG_SERIAL_PROBE_ALL=y + CONFIG_SPI=y + CONFIG_DM_SPI=y + CONFIG_NXP_FSPI=y +-# CONFIG_SYS_NXP_FSPI_AHB=y + CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y + CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +-CONFIG_DM_I2C=y +-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +-CONFIG_DM_RTC=y +-CONFIG_DM_GPIO=y + CONFIG_CMD_DATE=y +-CONFIG_RTC_PCF2127=y ++CONFIG_GIC_V3_ITS=y +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0017-lx2160acex7-misc-fixes-to-get-booting-from-eMMC-func.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0017-lx2160acex7-misc-fixes-to-get-booting-from-eMMC-func.patch new file mode 100644 index 00000000..053da1cf --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0017-lx2160acex7-misc-fixes-to-get-booting-from-eMMC-func.patch @@ -0,0 +1,70 @@ +From ce6a26cf0aa2af3a93b1183bd3543a9913e0656e Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 5 May 2020 01:01:01 +0300 +Subject: [PATCH 17/17] lx2160acex7: misc fixes to get booting from eMMC + functional + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + include/configs/lx2160a_common.h | 10 ++++++++++ + include/configs/lx2160acex7.h | 14 ++++++++------ + 2 files changed, 18 insertions(+), 6 deletions(-) + +diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h +index 91e9a2470f..f0c44a2368 100644 +--- a/include/configs/lx2160a_common.h ++++ b/include/configs/lx2160a_common.h +@@ -235,6 +235,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" + ++#define SD2_MC_INIT_CMD \ ++ "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \ ++ "mmc read 0x80e00000 0x7000 0x800;" \ ++ "env exists secureboot && " \ ++ "mmc read 0x80640000 0x3200 0x20 && " \ ++ "mmc read 0x80680000 0x3400 0x20 && " \ ++ "esbc_validate 0x80640000 && " \ ++ "esbc_validate 0x80680000 ;" \ ++ "fsl_mc start mc 0x80a00000 0x80e00000\0" ++ + #define EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ +diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h +index 7116e038a1..310168db47 100644 +--- a/include/configs/lx2160acex7.h ++++ b/include/configs/lx2160acex7.h +@@ -46,11 +46,6 @@ + + #endif + +-/* EMC2301 */ +-#define I2C_MUX_CH_EMC2301 0x01 +-#define I2C_EMC2301_ADDR 0x2f +-#define I2C_EMC2301_CMD 0x40 +-#define I2C_EMC2301_PWM 0x80 + + /* EEPROM */ + #undef CONFIG_ID_EEPROM /* Fixme */ +@@ -73,7 +68,14 @@ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ +- "mmc dev 0; mmcinfo; mmc read $load_addr " \ ++ "mmcinfo; mmc read $load_addr " \ ++ "$kernel_addr_sd $kernel_size_sd ;" \ ++ "env exists secureboot && mmc read $kernelheader_addr_r "\ ++ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ ++ " && esbc_validate ${kernelheader_addr_r};" \ ++ "bootm $load_addr#$BOARD\0" \ ++ "emmc_bootcmd=echo Trying load from emmc card..;" \ ++ "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq_2019.10.bbappend b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq_2019.10.bbappend new file mode 100644 index 00000000..40e6c38d --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq_2019.10.bbappend @@ -0,0 +1,22 @@ +FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:" + +SRC_URI_append_lx2160acex7 = "\ + file://0001-armv8-add-lx2160acex7-build-inclusion.patch \ + file://0002-armv8-lx2160acex-misc-hacks-to-get-the-sources-built.patch \ + file://0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch \ + file://0004-armv8-lx2160acex7-common-files-for-platform-support.patch \ + file://0005-armv8-lx2160acex7-lx2160acex-device-tree.patch \ + file://0006-armv8-lx2160acex7-board-support-files.patch \ + file://0007-lx2160a-load-dpl-into-0x80001000-instead-of-0x80d000.patch \ + file://0008-uboot-add-nvme-commands-and-for-distroboot.patch \ + file://0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch \ + file://0010-nvme-add-accessor-to-namespace-id-and-eui64.patch \ + file://0011-nvme-flush-dcache-on-both-r-w-and-the-prp-list.patch \ + file://0012-nvme-use-page-aligned-buffer-for-identify-command.patch \ + file://0013-lx2160a-cex7-move-from-lsdk-19.06-to-lsdk-19.09.patch \ + file://0014-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch \ + file://0015-lx2160a-cex7-set-mmc-dev-to-0-when-attempting-sd_boo.patch \ + file://0016-lx2160acex7-Misc-fixes-to-support-LSDK-20.04.patch \ + file://0017-lx2160acex7-misc-fixes-to-get-booting-from-eMMC-func.patch \ +" + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-boundary_2018.07.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-boundary_2018.07.bb index ef47d5f4..15542968 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-boundary_2018.07.bb +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-boundary_2018.07.bb @@ -42,4 +42,4 @@ addtask deploy after do_install before do_build FILES_${PN} += "/" -COMPATIBLE_MACHINE = "(nitrogen6x-lite|nitrogen6x|nitrogen6sx|nitrogen7|nitrogen8m)" +COMPATIBLE_MACHINE = "(nitrogen6x-lite|nitrogen6x|nitrogen6sx|nitrogen7|nitrogen8m|nitrogen8mm|nitrogen8mn)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-qoriq/boot.cmd.in b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-qoriq/boot.cmd.in new file mode 100644 index 00000000..d42efaf9 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-qoriq/boot.cmd.in @@ -0,0 +1,12 @@ +setenv kernel @KERNEL_IMAGETYPE@ +setenv fdt_file @KERNEL_DEVICETREE@ +setenv rootfs_mmc0 setenv rootfs /dev/mmcblk0p2 +setenv rootfs_mmc1 setenv rootfs /dev/mmcblk1p2 +setenv rootfs_nvme0 setenv rootfs /dev/nvme0n1p2 +setenv rootfs_scsi0 setenv rootfs /dev/sda2 +setenv rootfs_usb0 setenv rootfs /dev/sda2 +setenv rootfs_dhcp setenv rootfs /dev/root +run rootfs_${target} +setenv new_bootargs setenv bootargs console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 root=${rootfs} default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf +run new_bootargs +${bootfstype}load ${devtype} ${devnum}:1 ${kernel_addr_r} /${kernel}; ${bootfstype}load ${devtype} ${devnum}:1 ${fdt_addr_r} /${fdt_file}; @KERNEL_BOOTCMD@ ${kernel_addr_r} - ${fdt_addr_r} diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-qoriq_2019.10.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-qoriq_2019.10.bb new file mode 100644 index 00000000..eadd6832 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-qoriq_2019.10.bb @@ -0,0 +1,54 @@ +DESCRIPTION = "Boot script for launching images with U-Boot distro boot" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COREBASE}/meta/COPYING.MIT;md5=3da9cfbcb788c80a0384361b4de20420" + +INHIBIT_DEFAULT_DEPS = "1" +DEPENDS = "u-boot-mkimage-native" + +SRC_URI = "\ + file://boot.cmd.in \ +" + +KERNEL_BOOTCMD ?= "booti" + +inherit deploy + +do_configure[noexec] = "1" + +do_compile() { + kernel_devicetree_spc="" + kernel_devicetree_tmp="" + for kdt in ${KERNEL_DEVICETREE} + do + kernel_devicetree_tmp="${kernel_devicetree_tmp}${kernel_devicetree_spc}$(basename ${kdt})" + kernel_devicetree_spc=" " + done + kernel_devicetree="${kernel_devicetree_tmp}" + sed -e 's/@KERNEL_BOOTCMD[@]/${KERNEL_BOOTCMD}/' -e "s,@KERNEL_IMAGETYPE[@],${KERNEL_IMAGETYPE},g" \ + -e "s,@KERNEL_DEVICETREE[@],${kernel_devicetree},g" \ + "${WORKDIR}/boot.cmd.in" > ${B}/boot.cmd + target_arch="${TARGET_ARCH}" + test "${TARGET_ARCH}" = "aarch64" && target_arch="arm64" + mkimage -A ${target_arch} -T script -C none -n "Distro boot script" -d ${B}/boot.cmd ${B}/boot.scr +} + +do_install() { + install -Dm 0644 ${B}/boot.scr ${D}/boot/boot.scr +} + +do_deploy() { + install -Dm 0644 ${D}/boot/boot.scr ${DEPLOYDIR}/boot.scr-${MACHINE}-${PV}-${PR} + cd ${DEPLOYDIR} + rm -f boot.scr-${MACHINE} + ln -sf boot.scr-${MACHINE}-${PV}-${PR} boot.scr-${MACHINE} +} + +addtask deploy after do_install before do_build + +PROVIDES += "u-boot-default-script" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +COMPATIBLE_MACHINE = "(qoriq)" + +FILES_${PN} = "/boot" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-toradex/boot.cmd.in b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-toradex/boot.cmd.in new file mode 100644 index 00000000..5c514bad --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-toradex/boot.cmd.in @@ -0,0 +1,30 @@ +if test ${devtype} = "ubi" +then + echo "This script is not meant to distro boot from raw NAND flash." + exit +fi + +if test ${distro_bootpart} != 1 +then + echo "Boot partition needs to be the first partition" + exit +fi + +if test -n ${setup} +then + run setup +else + env set setupargs 'console=tty1 consoleblank=0' +fi +test -n ${m4boot} || env set m4boot ';' +test -n ${fdtfile} || env set fdtfile $fdt_file +test -n ${kernel_image} || env set kernel_image ${boot_file} + +env set uuid_set 'part uuid ${devtype} ${devnum}:2 uuid' +env set emmcargs_set 'env set emmcargs root=PARTUUID=${uuid} rw rootfstype=ext4 rootwait' +env set bootcmd_args 'env set bootargs ${defargs} ${emmcargs} ${setupargs} ${vidargs} ${tdxargs}' +env set bootcmd_kernel 'load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} ${kernel_image}' +env set bootcmd_dtb 'load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${fdtfile}' +env set bootcmd_run '@@KERNEL_BOOTCMD@@ ${kernel_addr_r} - ${fdt_addr_r}' +env set bootcmd 'run m4boot; run bootcmd_dtb && run uuid_set && run emmcargs_set && run bootcmd_args && run bootcmd_kernel && run bootcmd_run' +run bootcmd diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-toradex_2019.07.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-toradex_2019.07.bb new file mode 100644 index 00000000..a2aacdbb --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-script-toradex_2019.07.bb @@ -0,0 +1,45 @@ +DESCRIPTION = "Boot script for launching images with U-Boot distro boot" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COREBASE}/meta/COPYING.MIT;md5=3da9cfbcb788c80a0384361b4de20420" + +INHIBIT_DEFAULT_DEPS = "1" +DEPENDS = "u-boot-mkimage-native" + +SRC_URI = "\ + file://boot.cmd.in \ +" + +KERNEL_BOOTCMD ??= "bootz" +KERNEL_BOOTCMD_aarch64 ?= "booti" + +inherit deploy nopackages + +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +do_mkimage() { + sed -e 's/@@KERNEL_BOOTCMD@@/${KERNEL_BOOTCMD}/' \ + "${WORKDIR}/boot.cmd.in" > ${B}/boot.cmd + mkimage -T script -C none -n "Distro boot script" -d ${B}/boot.cmd ${B}/boot.scr +} + +addtask mkimage after do_compile before do_install + +do_install() { + install -Dm 0644 ${B}/boot.scr ${D}/boot.scr +} + +do_deploy() { + install -Dm 0644 ${D}/boot.scr ${DEPLOYDIR}/boot.scr-${MACHINE}-${PV}-${PR} + cd ${DEPLOYDIR} + rm -f boot.scr-${MACHINE} + ln -sf boot.scr-${MACHINE}-${PV}-${PR} boot.scr-${MACHINE} +} + +addtask deploy after do_install before do_build + +PROVIDES += "u-boot-default-script" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +COMPATIBLE_MACHINE = "(apalis-imx6|colibri-imx6|colibri-imx6ull|colibri-imx7-emmc|colibri-imx7-nand|colibri-vf)" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2016.11.inc b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-common.inc index dd8c9215..50319983 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2016.11.inc +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-common.inc @@ -1,19 +1,21 @@ # Copyright (C) 2015 Toradex AG -# Based on u-boot-fslc.inc Copyright (C) 2012-2014 O.S. Systems Software LTDA +# Based on u-boot-fslc.inc Copyright (C) 2012-2020 O.S. Systems Software LTDA # Released under the MIT license (see COPYING.MIT for the terms) SUMMARY = "U-Boot bootloader with support for Toradex Computer on Modules" LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" + +DEPENDS += "flex-native bison-native" SRC_URI = "git://git.toradex.com/u-boot-toradex.git;branch=${SRCBRANCH}" -SRCREV ?= "aca804c9ddadbf34a8ff82779e5598ec5e319f23" -SRCBRANCH ?= "2016.11-toradex" +SRCREV = "8f0e253cbceb940a3540e9ce73279a3e9a5a8528" +SRCBRANCH = "toradex_2019.07" S = "${WORKDIR}/git" -PV = "2016.11+git${SRCPV}" +PV = "2019.07+git${SRCPV}" PACKAGE_ARCH = "${MACHINE_ARCH}" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/0001-tools-fix-cross-compiling-tools-when-HOSTCC-is-overr.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/0001-tools-fix-cross-compiling-tools-when-HOSTCC-is-overr.patch deleted file mode 100644 index 2c087e85..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/0001-tools-fix-cross-compiling-tools-when-HOSTCC-is-overr.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 3b0825296aeba69c2cbfd3e179db2e9cbe5e70d7 Mon Sep 17 00:00:00 2001 -From: Masahiro Yamada <yamada.masahiro@socionext.com> -Date: Mon, 13 Mar 2017 17:43:16 +0900 -Subject: [PATCH] tools: fix cross-compiling tools when HOSTCC is overridden - -Upstream-Status: Backport - -Richard reported U-Boot tools issues in OpenEmbedded/Yocto project. - -OE needs to be able to change the default compiler. If we pass in -HOSTCC through the make command, it overwrites all HOSTCC instances, -including ones in tools/Makefile and tools/env/Makefile, which breaks -"make cross_tools" and "make env", respectively. - -Add "override" directives to avoid overriding HOSTCC instances that -really need to point to the cross-compiler. - -Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> -Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org> -Reviewed-by: Simon Glass <sjg@chromium.org> ---- - tools/Makefile | 2 +- - tools/env/Makefile | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/tools/Makefile b/tools/Makefile -index 1c840d7..a894b5c 100644 ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -262,7 +262,7 @@ $(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP) - subdir- += env - - ifneq ($(CROSS_BUILD_TOOLS),) --HOSTCC = $(CC) -+override HOSTCC = $(CC) - - quiet_cmd_crosstools_strip = STRIP $^ - cmd_crosstools_strip = $(STRIP) $^; touch $@ -diff --git a/tools/env/Makefile b/tools/env/Makefile -index 38ad118..95b28c0 100644 ---- a/tools/env/Makefile -+++ b/tools/env/Makefile -@@ -8,7 +8,7 @@ - # fw_printenv is supposed to run on the target system, which means it should be - # built with cross tools. Although it may look weird, we only replace "HOSTCC" - # with "CC" here for the maximum code reuse of scripts/Makefile.host. --HOSTCC = $(CC) -+override HOSTCC = $(CC) - - # Compile for a hosted environment on the target - HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \ --- -2.7.4 - diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils_2016.11.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils_2016.11.bb deleted file mode 100644 index 727c0a84..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils_2016.11.bb +++ /dev/null @@ -1,42 +0,0 @@ -require recipes-bsp/u-boot/u-boot-toradex_${PV}.inc - -SUMMARY = "U-Boot bootloader fw_printenv/setenv utilities" - -SRC_URI += "file://0001-tools-fix-cross-compiling-tools-when-HOSTCC-is-overr.patch \ - file://fw_env.config \ -" - -DEPENDS += "mtd-utils" - -INSANE_SKIP_${PN} = "already-stripped" -EXTRA_OEMAKE_class-target = 'CROSS_COMPILE=${TARGET_PREFIX} CC="${CC} ${CFLAGS} ${LDFLAGS}" HOSTCC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}" V=1' -EXTRA_OEMAKE_class-cross = 'ARCH=${TARGET_ARCH} CC="${CC} ${CFLAGS} ${LDFLAGS}" V=1' - -inherit uboot-config - -do_compile () { - oe_runmake ${UBOOT_MACHINE} - oe_runmake env -} - -do_install () { - install -d ${D}${base_sbindir} - install -d ${D}${sysconfdir} - install -m 755 ${S}/tools/env/fw_printenv ${D}${base_sbindir}/fw_printenv - install -m 755 ${S}/tools/env/fw_printenv ${D}${base_sbindir}/fw_setenv - install -m 0644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config -} - -do_install_class-cross () { - install -d ${D}${bindir_cross} - install -m 755 ${S}/tools/env/fw_printenv ${D}${bindir_cross}/fw_printenv - install -m 755 ${S}/tools/env/fw_printenv ${D}${bindir_cross}/fw_setenv -} - -SYSROOT_DIRS_append_class-cross = " ${bindir_cross}" - -PROVIDES += "u-boot-fw-utils" -RPROVIDES_${PN} += "u-boot-fw-utils" - -PACKAGE_ARCH = "${MACHINE_ARCH}" -BBCLASSEXTEND = "cross" diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/colibri-imx6ull/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/colibri-imx6ull/fw_env.config index 930bceee..930bceee 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/colibri-imx6ull/fw_env.config +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/colibri-imx6ull/fw_env.config diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/colibri-imx7-emmc/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/colibri-imx7-emmc/fw_env.config new file mode 100644 index 00000000..3c2ebb84 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/colibri-imx7-emmc/fw_env.config @@ -0,0 +1,17 @@ +# Configuration file for fw_(printenv/setenv) utility. +# Up to two entries are valid, in this case the redundant +# environment sector is assumed present. +# Device offset must be prefixed with 0x to be parsed as a hexadecimal value. +# On a block device a negative offset is treated as a backwards offset from the +# end of the device/partition, rather than a forwards offset from the start. + +# Colibri iMX7 Dual 1GB (eMMC) +# U-Boot environment is stored at the end of the first eMMC boot partition +# hence use a negative value. The environment is just in front of the config +# block which occupies the last sector (hence -0x200) +# Note that /dev/mmcblk0boot0 by default is read only +# To use fw_setenv you have to first make it writeable, on the cmdline e.g. by +# $ echo 0 > /sys/block/mmcblk0boot0/force_ro + +# Block device name Device offset Env. size +/dev/mmcblk0boot0 -0x2200 0x2000 diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/colibri-imx7/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/colibri-imx7/fw_env.config index b59116d4..b59116d4 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/colibri-imx7/fw_env.config +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/colibri-imx7/fw_env.config diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/fw_env.config index e054ccbb..e054ccbb 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/fw_env.config +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/fw_env.config diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/mx6/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/mx6/fw_env.config index a9e724e4..a9e724e4 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/mx6/fw_env.config +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/mx6/fw_env.config diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/vf/fw_env.config b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/vf/fw_env.config index 51f09d1d..51f09d1d 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex-fw-utils/vf/fw_env.config +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex/vf/fw_env.config diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2016.11.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2016.11.bb deleted file mode 100644 index e409131d..00000000 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2016.11.bb +++ /dev/null @@ -1,8 +0,0 @@ -require recipes-bsp/u-boot/u-boot.inc -require recipes-bsp/u-boot/u-boot-toradex_${PV}.inc - -LOCALVERSION = "-2.8.3" - -PROVIDES += "u-boot" - -inherit fsl-u-boot-localversion dtc-145 diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2019.07.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2019.07.bb new file mode 100644 index 00000000..6a1c71e6 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-toradex_2019.07.bb @@ -0,0 +1,31 @@ +require recipes-bsp/u-boot/u-boot.inc +require recipes-bsp/u-boot/u-boot-toradex-common.inc + +DEPENDS += "bc-native dtc-native" + +SRC_URI += "file://fw_env.config" + +PROVIDES += "u-boot" + +B = "${WORKDIR}/build" +do_configure[cleandirs] = "${B}" + +inherit fsl-u-boot-localversion + +# U-Boot is flashed 1k into a NAND block, create a binary which prepends +# U-boot with 1k of zeros to ease flashing +nand_padding () { + dd bs=1024 count=1 if=/dev/zero | cat - u-boot.imx > u-boot-nand.imx +} + +do_compile_append_colibri-imx6ull () { + nand_padding +} + +do_compile_append_colibri-imx7 () { + nand_padding +} + +do_compile_append_colibri-vf () { + nand_padding +} diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-variscite/0001-Fix-build-with-recent-layers.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-variscite/0001-Fix-build-with-recent-layers.patch new file mode 100644 index 00000000..dba4dc18 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-variscite/0001-Fix-build-with-recent-layers.patch @@ -0,0 +1,34 @@ +From 8c3356f5328d3e48709ed7483564a1cd79e387cf Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Andreas=20M=C3=BCller?= <schnitzeltony@gmail.com> +Date: Fri, 3 Jan 2020 14:04:46 +0100 +Subject: [PATCH] Fix build with recent layers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Fixes: +arm-mortsgna-linux-gnueabi-ld.bfd: error: linker script file '<workdir>/git/arch/arm/lib/elf_arm_efi.lds' appears multiple times + +Upstream-Status: Pending + +Signed-off-by: Andreas Müller <schnitzeltony@gmail.com> +--- + scripts/Makefile.lib | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 23be324369..a32daa4394 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -377,8 +377,6 @@ cmd_efi_ld = $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared \ + + EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS) + +-$(obj)/helloworld.so: $(EFI_LDS_PATH) +- + $(obj)/helloworld.so: $(obj)/helloworld.o arch/$(ARCH)/lib/$(EFI_CRT0) \ + arch/$(ARCH)/lib/$(EFI_RELOC) + $(call cmd,efi_ld) +-- +2.21.0 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-variscite_2017.03.bb b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-variscite_2017.03.bb index 818e03e4..c529e56a 100644 --- a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-variscite_2017.03.bb +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-variscite_2017.03.bb @@ -5,15 +5,19 @@ LICENSE = "GPLv2+" LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" COMPATIBLE_MACHINE = "(imx6qdl-variscite-som)" +DEPENDS += "bc-native" +UBOOT_INITIAL_ENV = "" + PROVIDES += "u-boot" SPL_BINARY = "SPL" -SRCREV = "3b5f889cb501c9fbe44c750c657dcd9ea4875176" +SRCREV = "a7869c2cde98e5f5b1886d8f54dff321a7aa0597" SRCBRANCH = "imx_v2017.03_4.9.11_1.0.0_ga_var01" SRC_URI = "\ git://github.com/varigit/uboot-imx.git;protocol=git;branch=${SRCBRANCH} \ + file://0001-Fix-build-with-recent-layers.patch \ " S = "${WORKDIR}/git" |