Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

11 files changed, 403 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am64_hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_hardware.h
new file mode 100644
index 000000000..c368aa7e6
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM64 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM64_HARDWARE_H
+#define __ASM_ARCH_AM64_HARDWARE_H
+
+#include <config.h>
+
+#define CTRL_MMR0_BASE					0x43000000
+#define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
+
+#define PADCFG_MMR1_BASE				0xf0000
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK		0x00000078
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT		3
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK		0x00000380
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT		7
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK		0x00001c00
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT		10
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK		0x00002000
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT		13
+
+/* After the cfg mask and shifts have been applied */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT		2
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK		0x04
+
+/*
+ * The CTRL_MMR and PADCFG_MMR memory space is divided into several
+ * equally-spaced partitions, so defining the partition size allows us to
+ * determine register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE			0x4000
+
+/*
+ * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0				0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL			0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK		BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT		0
+#define CTRLMMR_LOCK_KICK1				0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL			0xd172bc5a
+
+#define ROM_ENTENDED_BOOT_DATA_INFO			0x701beb00
+
+/* Use Last 1K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START		0x701bfc00
+
+#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am64_spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_spl.h
new file mode 100644
index 000000000..36826cfc4
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ */
+#ifndef _ASM_ARCH_AM64_SPL_H_
+#define _ASM_ARCH_AM64_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM			0x00
+#define BOOT_DEVICE_OSPI		0x01
+#define BOOT_DEVICE_QSPI		0x02
+#define BOOT_DEVICE_SPI			0x03
+#define BOOT_DEVICE_ETHERNET		0x04
+#define BOOT_DEVICE_ETHERNET_RGMII	0x04
+#define BOOT_DEVICE_ETHERNET_RMII	0x05
+#define BOOT_DEVICE_I2C			0x06
+#define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_MMC			0x08
+#define BOOT_DEVICE_EMMC		0x09
+
+#define BOOT_DEVICE_USB			0x0A
+#define BOOT_DEVICE_GPMC_NOR		0x0C
+#define BOOT_DEVICE_PCIE		0x0D
+#define BOOT_DEVICE_XSPI		0x0E
+
+#define BOOT_DEVICE_NOBOOT		0x0F
+
+#define BOOT_DEVICE_MMC2		0x08
+#define BOOT_DEVICE_MMC1		0x09
+/* INVALID */
+#define BOOT_DEVICE_MMC2_2		0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_USB		0x01
+#define BACKUP_BOOT_DEVICE_UART		0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET	0x04
+#define BACKUP_BOOT_DEVICE_MMC		0x05
+#define BACKUP_BOOT_DEVICE_SPI		0x06
+#define BACKUP_BOOT_DEVICE_I2C		0x07
+
+#define K3_PRIMARY_BOOTMODE		0x0
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am6_hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_hardware.h
new file mode 100644
index 000000000..1908a13f0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM6 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM6_HARDWARE_H
+#define __ASM_ARCH_AM6_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define CTRL_MMR0_BASE					0x00100000
+#define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
+
+#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK		GENMASK(3, 0)
+#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT		0
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK		GENMASK(6, 4)
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT	4
+#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK		GENMASK(12, 12)
+#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT		12
+#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK		GENMASK(14, 14)
+#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT		14
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK		GENMASK(17, 17)
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT	12
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT		9
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK		GENMASK(10, 9)
+
+#define WKUP_CTRL_MMR0_BASE				0x43000000
+#define MCU_CTRL_MMR0_BASE				0x40f00000
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE			0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
+ * shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0				0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL			0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK		BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT		0
+#define CTRLMMR_LOCK_KICK1				0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL			0xd172bc5a
+
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
+#endif /* __ASM_ARCH_AM6_HARDWARE_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am6_spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_spl.h
new file mode 100644
index 000000000..61e038092
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_spl.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_AM6_SPL_H_
+#define _ASM_ARCH_AM6_SPL_H_
+
+#define BOOT_DEVICE_RAM			0x00
+#define BOOT_DEVICE_OSPI		0x01
+#define BOOT_DEVICE_QSPI		0x02
+#define BOOT_DEVICE_HYPERFLASH		0x03
+#define BOOT_DEVICE_SPI			0x04
+#define BOOT_DEVICE_I2C			0x05
+#define BOOT_DEVICE_MMC2		0x06
+#define BOOT_DEVICE_ETHERNET		0x07
+#define BOOT_DEVICE_DFU			0x08
+#define BOOT_DEVICE_USB			0x408
+#define BOOT_DEVICE_PCIE		0x09
+#define BOOT_DEVICE_UART		0x0a
+#define BOOT_DEVICE_NAND		0x0c
+#define BOOT_DEVICE_MMC1		0x0d
+#define BOOT_DEVICE_MMC2_2		0x0e
+
+#define BACKUP_BOOT_DEVICE_RAM		0x0
+#define BACKUP_BOOT_DEVICE_USB		0x1
+#define BACKUP_BOOT_DEVICE_UART		0x2
+#define BACKUP_BOOT_DEVICE_ETHERNET	0x3
+#define BACKUP_BOOT_DEVICE_MMC2		0x4
+#define BACKUP_BOOT_DEVICE_SPI		0x5
+#define BACKUP_BOOT_DEVICE_HYPERFLASH	0x6
+#define BACKUP_BOOT_DEVICE_I2C		0x7
+
+#define K3_PRIMARY_BOOTMODE		0x0
+#define K3_BACKUP_BOOTMODE		0x1
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/clock.h b/roms/u-boot/arch/arm/mach-k3/include/mach/clock.h
new file mode 100644
index 000000000..e3adbcd9d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/clock.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: Common SoC clock definitions.
+ *
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <config.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000
+#define V_SCLK				V_OSCK
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/hardware.h
new file mode 100644
index 000000000..8725e7d51
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/hardware.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_HARDWARE_H_
+#define _ASM_ARCH_HARDWARE_H_
+
+#ifdef CONFIG_SOC_K3_AM6
+#include "am6_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_hardware.h"
+#endif
+
+/* Assuming these addresses and definitions stay common across K3 devices */
+#define CTRLMMR_WKUP_JTAG_ID	0x43000014
+#define JTAG_ID_VARIANT_SHIFT	28
+#define JTAG_ID_VARIANT_MASK	(0xf << 28)
+#define JTAG_ID_PARTNO_SHIFT	12
+#define JTAG_ID_PARTNO_MASK	(0xffff << 12)
+
+#define K3_ROM_BOOT_HEADER_MAGIC	"EXTBOOT"
+
+struct rom_extended_boot_data {
+	char header[8];
+	u32 num_components;
+};
+
+#endif /* _ASM_ARCH_HARDWARE_H_ */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_hardware.h
new file mode 100644
index 000000000..b98f0a82f
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J721E SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_J721E_HARDWARE_H
+#define __ASM_ARCH_J721E_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define CTRL_MMR0_BASE					0x00100000
+#define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
+
+#define MAIN_DEVSTAT_BOOT_MODE_B_MASK		BIT(0)
+#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT		0
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK		GENMASK(3, 1)
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT	1
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK	BIT(6)
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT		6
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK			BIT(7)
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT		7
+
+#define WKUP_CTRL_MMR0_BASE				0x43000000
+#define MCU_CTRL_MMR0_BASE				0x40f00000
+
+#define CTRLMMR_WKUP_DEVSTAT			(WKUP_CTRL_MMR0_BASE + 0x30)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK	GENMASK(5, 3)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT	3
+#define WKUP_DEVSTAT_MCU_OMLY_MASK		BIT(6)
+#define WKUP_DEVSTAT_MCU_ONLY_SHIFT		6
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE			0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
+ * shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0				0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL			0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK		BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT		0
+#define CTRLMMR_LOCK_KICK1				0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL			0xd172bc5a
+
+/* ROM HANDOFF Structure location */
+#define ROM_ENTENDED_BOOT_DATA_INFO			0x41cffb00
+
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
+#endif /* __ASM_ARCH_J721E_HARDWARE_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_spl.h
new file mode 100644
index 000000000..e8947917a
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_J721E_SPL_H_
+#define _ASM_ARCH_J721E_SPL_H_
+
+/* With BootMode B = 0 */
+#include <linux/bitops.h>
+#define BOOT_DEVICE_HYPERFLASH		0x00
+#define BOOT_DEVICE_OSPI		0x01
+#define BOOT_DEVICE_QSPI		0x02
+#define BOOT_DEVICE_SPI			0x03
+#define BOOT_DEVICE_ETHERNET		0x04
+#define BOOT_DEVICE_I2C			0x06
+#define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_NOR			BOOT_DEVICE_HYPERFLASH
+
+/* With BootMode B = 1 */
+#define BOOT_DEVICE_MMC2		0x10
+#define BOOT_DEVICE_MMC1		0x11
+#define BOOT_DEVICE_DFU			0x12
+#define BOOT_DEVICE_UFS			0x13
+#define BOOT_DEVIE_GPMC			0x14
+#define BOOT_DEVICE_PCIE		0x15
+#define BOOT_DEVICE_MMC2_2		0x16
+#define BOOT_DEVICE_RAM			0x17
+
+/* Backup boot modes with MCU Only = 0 */
+#define BACKUP_BOOT_DEVICE_RAM		0x0
+#define BACKUP_BOOT_DEVICE_USB		0x1
+#define BACKUP_BOOT_DEVICE_UART		0x3
+#define BACKUP_BOOT_DEVICE_ETHERNET	0x4
+#define BACKUP_BOOT_DEVICE_MMC2		0x5
+#define BACKUP_BOOT_DEVICE_SPI		0x6
+#define BACKUP_BOOT_DEVICE_I2C		0x7
+
+#define BOOT_MODE_B_SHIFT		4
+#define BOOT_MODE_B_MASK		BIT(4)
+
+#define K3_PRIMARY_BOOTMODE		0x0
+#define K3_BACKUP_BOOTMODE		0x1
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/spl.h
new file mode 100644
index 000000000..ef1c3fb8c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/spl.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#ifdef CONFIG_SOC_K3_AM6
+#include "am6_spl.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_spl.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_spl.h"
+#endif
+#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/sys_proto.h b/roms/u-boot/arch/arm/mach-k3/include/mach/sys_proto.h
new file mode 100644
index 000000000..60287b261
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/sys_proto.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+		  u32 bound);
+struct ti_sci_handle *get_ti_sci_handle(void);
+int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
+int do_board_detect(void);
+void release_resources_for_core_shutdown(void);
+int fdt_disable_node(void *blob, char *node_path);
+
+bool soc_is_j721e(void);
+bool soc_is_j7200(void);
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/sysfw-loader.h b/roms/u-boot/arch/arm/mach-k3/include/mach/sysfw-loader.h
new file mode 100644
index 000000000..b23a9e821
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/sysfw-loader.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#ifndef _SYSFW_LOADER_H_
+#define _SYSFW_LOADER_H_
+
+void k3_sysfw_loader(bool rom_loaded_sysfw,
+		     void (*config_pm_pre_callback)(void),
+		     void (*config_pm_done_callback)(void));
+
+#endif