diff options
Diffstat (limited to 'roms/u-boot/board/atmel')
87 files changed, 5027 insertions, 0 deletions
diff --git a/roms/u-boot/board/atmel/at91rm9200ek/Kconfig b/roms/u-boot/board/atmel/at91rm9200ek/Kconfig new file mode 100644 index 000000000..952351dcd --- /dev/null +++ b/roms/u-boot/board/atmel/at91rm9200ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91RM9200EK + +config SYS_BOARD + default "at91rm9200ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91rm9200ek" + +endif diff --git a/roms/u-boot/board/atmel/at91rm9200ek/MAINTAINERS b/roms/u-boot/board/atmel/at91rm9200ek/MAINTAINERS new file mode 100644 index 000000000..b25bc5802 --- /dev/null +++ b/roms/u-boot/board/atmel/at91rm9200ek/MAINTAINERS @@ -0,0 +1,7 @@ +AT91RM9200EK BOARD +M: Andreas Bießmann <andreas@biessmann.org> +S: Maintained +F: board/atmel/at91rm9200ek/ +F: include/configs/at91rm9200ek.h +F: configs/at91rm9200ek_defconfig +F: configs/at91rm9200ek_ram_defconfig diff --git a/roms/u-boot/board/atmel/at91rm9200ek/Makefile b/roms/u-boot/board/atmel/at91rm9200ek/Makefile new file mode 100644 index 000000000..2d5c28082 --- /dev/null +++ b/roms/u-boot/board/atmel/at91rm9200ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += at91rm9200ek.o +obj-y += led.o diff --git a/roms/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c b/roms/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c new file mode 100644 index 000000000..a314ced5e --- /dev/null +++ b/roms/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010 Andreas Bießmann <andreas@biessmann.org> + * + * derived from previous work + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + */ + +#include <common.h> +#include <init.h> +#include <net.h> +#include <netdev.h> +#include <asm/global_data.h> +#include <asm/mach-types.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_common.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +int board_init(void) +{ + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + + /* + * Correct IRDA resistor problem + * Set PA23_TXD in Output + */ + writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer); + + /* arch number of AT91RM9200EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + +int dram_init (void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(struct bd_info *bis) +{ + return at91emac_register(bis, (u32) ATMEL_BASE_EMAC); +} +#endif diff --git a/roms/u-boot/board/atmel/at91rm9200ek/led.c b/roms/u-boot/board/atmel/at91rm9200ek/led.c new file mode 100644 index 000000000..a6b4d1fb6 --- /dev/null +++ b/roms/u-boot/board/atmel/at91rm9200ek/led.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2006 + * Atmel Nordic AB <www.atmel.com> + * Ulf Samuelsson <ulf@atmel.com> + * + * (C) Copyright 2010 + * Andreas Bießmann <andreas@biessmann.org> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> +#include <asm/arch/at91_pio.h> +#include <status_led.h> + +/* bit mask in PIO port B */ +#define GREEN_LED (1<<0) +#define YELLOW_LED (1<<1) +#define RED_LED (1<<2) + +void green_led_on(void) +{ + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + writel(GREEN_LED, &pio->piob.codr); +} + +void yellow_led_on(void) +{ + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + writel(YELLOW_LED, &pio->piob.codr); +} + +void red_led_on(void) +{ + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + writel(RED_LED, &pio->piob.codr); +} + +void green_led_off(void) +{ + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + writel(GREEN_LED, &pio->piob.sodr); +} + +void yellow_led_off(void) +{ + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + writel(YELLOW_LED, &pio->piob.sodr); +} + +void red_led_off(void) +{ + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + writel(RED_LED, &pio->piob.sodr); +} + +void coloured_LED_init (void) +{ + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + + at91_periph_clk_enable(ATMEL_ID_PIOB); + + /* Disable peripherals on LEDs */ + writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per); + /* Enable pins as outputs */ + writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer); + /* Turn all LEDs OFF */ + writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr); +} diff --git a/roms/u-boot/board/atmel/at91sam9260ek/Kconfig b/roms/u-boot/board/atmel/at91sam9260ek/Kconfig new file mode 100644 index 000000000..3844f086b --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9260ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91SAM9260EK + +config SYS_BOARD + default "at91sam9260ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91sam9260ek" + +endif diff --git a/roms/u-boot/board/atmel/at91sam9260ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9260ek/MAINTAINERS new file mode 100644 index 000000000..aa7898ef7 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9260ek/MAINTAINERS @@ -0,0 +1,17 @@ +AT91SAM9260EK BOARD +M: Stelian Pop <stelian@popies.net> +S: Maintained +F: board/atmel/at91sam9260ek/ +F: include/configs/at91sam9260ek.h +F: configs/at91sam9260ek_dataflash_cs0_defconfig +F: configs/at91sam9260ek_dataflash_cs1_defconfig +F: configs/at91sam9260ek_nandflash_defconfig +F: configs/at91sam9g20ek_2mmc_nandflash_defconfig +F: configs/at91sam9g20ek_dataflash_cs0_defconfig +F: configs/at91sam9g20ek_dataflash_cs1_defconfig +F: configs/at91sam9g20ek_mmc_defconfig +F: configs/at91sam9g20ek_2mmc_defconfig +F: configs/at91sam9g20ek_nandflash_defconfig +F: configs/at91sam9xeek_dataflash_cs0_defconfig +F: configs/at91sam9xeek_dataflash_cs1_defconfig +F: configs/at91sam9xeek_nandflash_defconfig diff --git a/roms/u-boot/board/atmel/at91sam9260ek/Makefile b/roms/u-boot/board/atmel/at91sam9260ek/Makefile new file mode 100644 index 000000000..56cac9750 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9260ek/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> + +obj-y += at91sam9260ek.o +obj-$(CONFIG_AT91_LED) += led.o diff --git a/roms/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c b/roms/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c new file mode 100644 index 000000000..38f97bce2 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <net.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void at91sam9260ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + at91sam9260ek_nand_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif diff --git a/roms/u-boot/board/atmel/at91sam9260ek/led.c b/roms/u-boot/board/atmel/at91sam9260ek/led.c new file mode 100644 index 000000000..cc6d5d7a0 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9260ek/led.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <status_led.h> + +void coloured_LED_init(void) +{ + /* Clock is enabled in board_early_init_f() */ + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); +} diff --git a/roms/u-boot/board/atmel/at91sam9261ek/Kconfig b/roms/u-boot/board/atmel/at91sam9261ek/Kconfig new file mode 100644 index 000000000..2971b3cf9 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9261ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91SAM9261EK + +config SYS_BOARD + default "at91sam9261ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91sam9261ek" + +endif diff --git a/roms/u-boot/board/atmel/at91sam9261ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9261ek/MAINTAINERS new file mode 100644 index 000000000..682dfdfbf --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9261ek/MAINTAINERS @@ -0,0 +1,11 @@ +AT91SAM9261EK BOARD +M: Stelian Pop <stelian@popies.net> +S: Maintained +F: board/atmel/at91sam9261ek/ +F: include/configs/at91sam9261ek.h +F: configs/at91sam9261ek_dataflash_cs0_defconfig +F: configs/at91sam9261ek_dataflash_cs3_defconfig +F: configs/at91sam9261ek_nandflash_defconfig +F: configs/at91sam9g10ek_dataflash_cs0_defconfig +F: configs/at91sam9g10ek_dataflash_cs3_defconfig +F: configs/at91sam9g10ek_nandflash_defconfig diff --git a/roms/u-boot/board/atmel/at91sam9261ek/Makefile b/roms/u-boot/board/atmel/at91sam9261ek/Makefile new file mode 100644 index 000000000..7f5369f43 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9261ek/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> + +obj-y += at91sam9261ek.o +obj-$(CONFIG_AT91_LED) += led.o diff --git a/roms/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c b/roms/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c new file mode 100644 index 000000000..0318eeaa9 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/at91sam9261_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <lcd.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) +#include <net.h> +#include <netdev.h> +#endif +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void at91sam9261ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ +#ifdef CONFIG_AT91SAM9G10EK + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); +#else + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); +#endif + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +static void at91sam9261ek_dm9000_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + /* Configure SMC CS2 for DM9000 */ +#ifdef CONFIG_AT91SAM9G10EK + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); +#else + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); +#endif + + /* Configure Reset signal as output */ + at91_set_gpio_output(AT91_PIN_PC10, 0); + + /* Configure Interrupt pin as input, no pull-up */ + at91_set_gpio_input(AT91_PIN_PC11, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ +} + +static void at91sam9261ek_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ + + at91_system_clk_enable(AT91_PMC_HCK1); + + /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */ +#ifdef CONFIG_AT91SAM9261EK + gd->fb_base = ATMEL_BASE_SRAM; +#endif +} + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + ATMEL_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += get_nand_dev_by_index(i)->size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_AT91SAM9G10EK + /* arch number of AT91SAM9G10EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK; +#else + /* arch number of AT91SAM9261EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; +#endif + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + at91sam9261ek_nand_hw_init(); +#endif +#ifdef CONFIG_DRIVER_DM9000 + at91sam9261ek_dm9000_hw_init(); +#endif +#ifdef CONFIG_LCD + at91sam9261ek_lcd_hw_init(); +#endif + return 0; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(struct bd_info *bis) +{ + return dm9000_initialize(bis); +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_DRIVER_DM9000 + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(); +#endif +} +#endif diff --git a/roms/u-boot/board/atmel/at91sam9261ek/led.c b/roms/u-boot/board/atmel/at91sam9261ek/led.c new file mode 100644 index 000000000..a1aab98d5 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9261ek/led.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <status_led.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/clk.h> +#include <asm/io.h> + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_PIOA); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); +} diff --git a/roms/u-boot/board/atmel/at91sam9263ek/Kconfig b/roms/u-boot/board/atmel/at91sam9263ek/Kconfig new file mode 100644 index 000000000..3f0873fe5 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9263ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91SAM9263EK + +config SYS_BOARD + default "at91sam9263ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91sam9263ek" + +endif diff --git a/roms/u-boot/board/atmel/at91sam9263ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9263ek/MAINTAINERS new file mode 100644 index 000000000..3b4b654bf --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9263ek/MAINTAINERS @@ -0,0 +1,10 @@ +AT91SAM9263EK BOARD +M: Stelian Pop <stelian@popies.net> +S: Maintained +F: board/atmel/at91sam9263ek/ +F: include/configs/at91sam9263ek.h +F: configs/at91sam9263ek_dataflash_defconfig +F: configs/at91sam9263ek_dataflash_cs0_defconfig +F: configs/at91sam9263ek_nandflash_defconfig +F: configs/at91sam9263ek_norflash_defconfig +F: configs/at91sam9263ek_norflash_boot_defconfig diff --git a/roms/u-boot/board/atmel/at91sam9263ek/Makefile b/roms/u-boot/board/atmel/at91sam9263ek/Makefile new file mode 100644 index 000000000..44c8d95a0 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9263ek/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> + +obj-y += at91sam9263ek.o +obj-$(CONFIG_AT91_LED) += led.o diff --git a/roms/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c b/roms/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c new file mode 100644 index 000000000..3218e14e8 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <flash.h> +#include <init.h> +#include <net.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <linux/sizes.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/clk.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hardware.h> +#include <lcd.h> +#include <atmel_lcdc.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void at91sam9263ek_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Enable CS3 */ + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOCDE); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ + at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */ +} + +static void at91sam9263ek_lcd_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); + gd->fb_base = ATMEL_BASE_SRAM0; +} + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +#ifdef CONFIG_MTD_NOR_FLASH +extern flash_info_t flash_info[]; +#endif + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; +#ifdef CONFIG_MTD_NOR_FLASH + ulong flash_size; +#endif + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + ATMEL_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += get_nand_dev_by_index(i)->size; +#ifdef CONFIG_MTD_NOR_FLASH + flash_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) + flash_size += flash_info[i].size; +#endif + lcd_printf (" %ld MB SDRAM, %ld MB NAND", + dram_size >> 20, + nand_size >> 20 ); +#ifdef CONFIG_MTD_NOR_FLASH + lcd_printf (",\n %ld MB NOR", + flash_size >> 20); +#endif + lcd_puts ("\n"); +} +#endif /* CONFIG_LCD_INFO */ +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* arch number of AT91SAM9263EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + at91sam9263ek_nand_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + at91sam9263ek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif diff --git a/roms/u-boot/board/atmel/at91sam9263ek/led.c b/roms/u-boot/board/atmel/at91sam9263ek/led.c new file mode 100644 index 000000000..849501ec3 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9263ek/led.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <status_led.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/clk.h> + +void coloured_LED_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOB); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); +} diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/Kconfig b/roms/u-boot/board/atmel/at91sam9m10g45ek/Kconfig new file mode 100644 index 000000000..211c411ef --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91SAM9M10G45EK + +config SYS_BOARD + default "at91sam9m10g45ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91sam9m10g45ek" + +endif diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9m10g45ek/MAINTAINERS new file mode 100644 index 000000000..54632c36d --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/MAINTAINERS @@ -0,0 +1,7 @@ +AT91SAM9M10G45EK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/at91sam9m10g45ek/ +F: include/configs/at91sam9m10g45ek.h +F: configs/at91sam9m10g45ek_mmc_defconfig +F: configs/at91sam9m10g45ek_nandflash_defconfig diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/Makefile b/roms/u-boot/board/atmel/at91sam9m10g45ek/Makefile new file mode 100644 index 000000000..b05b81bac --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> + +obj-y += at91sam9m10g45ek.o +obj-(CONFIG_AT91_LED) += led.o diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/roms/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c new file mode 100644 index 000000000..8cb2808e0 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <net.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/at91sam9g45_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <lcd.h> +#include <linux/mtd/rawnand.h> +#include <atmel_lcdc.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +void at91sam9m10g45ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ + /* + * On the at91sam9m10g45ek board, the chip wm9711 stays in the + * test mode, so it needs do some action to exit test mode. + */ + at91_periph_clk_enable(ATMEL_ID_PIODE); + at91_set_gpio_output(AT91_PIN_PD7, 0); + at91_set_gpio_output(AT91_PIN_PD8, 0); + at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); + at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); + +#ifdef CONFIG_SD_BOOT + at91_mci_hw_init(); +#elif CONFIG_NAND_BOOT + at91sam9m10g45ek_nand_hw_init(); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_DQMS_SHARED | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3); + + ddr2->rtr = 0x24b; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ + 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ + 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct atmel_mpddrc_config ddr2; + + ddr2_conf(&ddr2); + + at91_system_clk_enable(AT91_PMC_DDR); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); +} +#endif + +#ifdef CONFIG_CMD_USB +static void at91sam9m10g45ek_usb_hw_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIODE); + + at91_set_gpio_output(AT91_PIN_PD1, 0); + at91_set_gpio_output(AT91_PIN_PD3, 0); +} +#endif + +#ifdef CONFIG_LCD + +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | + ATMEL_LCDC_INVFRAME_NORMAL, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 45, + .vl_left_margin = 1, + .vl_right_margin = 1, + .vl_vsync_len = 1, + .vl_upper_margin = 40, + .vl_lower_margin = 1, + .mmio = ATMEL_BASE_LCDC, +}; + + +void lcd_enable(void) +{ + at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ +} + +static void at91sam9m10g45ek_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ + + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); + + gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; +} + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + ATMEL_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += get_nand_dev_by_index(i)->size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* arch number of AT91SAM9M10G45EK-Board */ +#ifdef CONFIG_AT91SAM9M10G45EK + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; +#elif defined CONFIG_AT91SAM9G45EKES + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; +#endif + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + at91sam9m10g45ek_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + at91sam9m10g45ek_usb_hw_init(); +#endif +#ifdef CONFIG_LCD + at91sam9m10g45ek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/led.c b/roms/u-boot/board/atmel/at91sam9m10g45ek/led.c new file mode 100644 index 000000000..f44a09623 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/led.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <status_led.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> + +void coloured_LED_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIODE); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); +} diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/Kconfig b/roms/u-boot/board/atmel/at91sam9n12ek/Kconfig new file mode 100644 index 000000000..816003a5d --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9n12ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91SAM9N12EK + +config SYS_BOARD + default "at91sam9n12ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91sam9n12ek" + +endif diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9n12ek/MAINTAINERS new file mode 100644 index 000000000..0d33340d8 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9n12ek/MAINTAINERS @@ -0,0 +1,8 @@ +AT91SAM9N12EK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/at91sam9n12ek/ +F: include/configs/at91sam9n12ek.h +F: configs/at91sam9n12ek_mmc_defconfig +F: configs/at91sam9n12ek_nandflash_defconfig +F: configs/at91sam9n12ek_spiflash_defconfig diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/Makefile b/roms/u-boot/board/atmel/at91sam9n12ek/Makefile new file mode 100644 index 000000000..2ca5459a1 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9n12ek/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2013 +# Josh Wu <josh.wu@atmel.com> +# Atmel corporation <www.atmel.com> + +obj-y += at91sam9n12ek.o diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/roms/u-boot/board/atmel/at91sam9n12ek/at91sam9n12ek.c new file mode 100644 index 000000000..a3fc55bbc --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2013 Atmel Corporation + * Josh Wu <josh.wu@atmel.com> + */ + +#include <common.h> +#include <init.h> +#include <net.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/clk.h> +#include <debug_uart.h> +#include <lcd.h> +#include <atmel_hlcdc.h> +#include <netdev.h> + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ +#ifdef CONFIG_NAND_ATMEL +static void at91sam9n12ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + /* Configure databus */ + csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */ + /* Configure IO drive */ + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + /* Configure RDY/BSY pin */ + at91_set_pio_input(AT91_PIO_PORTD, 5, 1); + + /* Configure ENABLE pin for NandFlash */ + at91_set_pio_output(AT91_PIO_PORTD, 4, 1); + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_bpix = LCD_BPP, + .vl_sync = 0, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 8, + .vl_right_margin = 43, + .vl_vsync_len = 10, + .vl_upper_margin = 4, + .vl_lower_margin = 12, + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ + at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */ +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_printf("ATMEL Corp\n"); + lcd_printf("at91@atmel.com\n"); + lcd_printf("%s CPU at %s MHz\n", + ATMEL_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += get_nand_dev_by_index(i)->size; + lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */ + +#ifdef CONFIG_KS8851_MLL +void at91sam9n12ek_ks8851_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | + AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); + + /* Configure NCS2 PIN */ + at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); +} +#endif + +#ifdef CONFIG_USB_ATMEL +void at91sam9n12ek_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTB, 7, 0); +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + at91sam9n12ek_nand_hw_init(); +#endif + +#ifdef CONFIG_LCD + at91_lcd_hw_init(); +#endif + +#ifdef CONFIG_KS8851_MLL + at91sam9n12ek_ks8851_hw_init(); +#endif + +#ifdef CONFIG_USB_ATMEL + at91sam9n12ek_usb_hw_init(); +#endif + + return 0; +} + +#ifdef CONFIG_KS8851_MLL +int board_eth_init(struct bd_info *bis) +{ + return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + at91_mci_hw_init(); +#elif CONFIG_NAND_BOOT + at91sam9n12ek_nand_hw_init(); +#elif CONFIG_SPI_BOOT + at91_spi0_hw_init(1 << 4); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddrc_config ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(AT91_PMC_DDR, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); +} +#endif diff --git a/roms/u-boot/board/atmel/at91sam9rlek/Kconfig b/roms/u-boot/board/atmel/at91sam9rlek/Kconfig new file mode 100644 index 000000000..81a839ac0 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9rlek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91SAM9RLEK + +config SYS_BOARD + default "at91sam9rlek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91sam9rlek" + +endif diff --git a/roms/u-boot/board/atmel/at91sam9rlek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9rlek/MAINTAINERS new file mode 100644 index 000000000..ca8c0b158 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9rlek/MAINTAINERS @@ -0,0 +1,8 @@ +AT91SAM9RLEK BOARD +M: Stelian Pop <stelian@popies.net> +S: Maintained +F: board/atmel/at91sam9rlek/ +F: include/configs/at91sam9rlek.h +F: configs/at91sam9rlek_dataflash_defconfig +F: configs/at91sam9rlek_nandflash_defconfig +F: configs/at91sam9rlek_mmc_defconfig diff --git a/roms/u-boot/board/atmel/at91sam9rlek/Makefile b/roms/u-boot/board/atmel/at91sam9rlek/Makefile new file mode 100644 index 000000000..30dcb4913 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9rlek/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> + +obj-y += at91sam9rlek.o +obj-$(CONFIG_AT91_LED) += led.o diff --git a/roms/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c b/roms/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c new file mode 100644 index 000000000..f427ee658 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/arch/at91sam9rl.h> +#include <asm/arch/at91sam9rl_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> + +#include <lcd.h> +#include <atmel_lcdc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void at91sam9rlek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOD); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ +} +static void at91sam9rlek_lcd_hw_init(void) +{ + at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ + at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ + at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ + at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ + at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ + at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ + at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + ATMEL_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += get_nand_dev_by_index(i)->size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* arch number of AT91SAM9RLEK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + at91sam9rlek_nand_hw_init(); +#endif +#ifdef CONFIG_LCD + at91sam9rlek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/roms/u-boot/board/atmel/at91sam9rlek/led.c b/roms/u-boot/board/atmel/at91sam9rlek/led.c new file mode 100644 index 000000000..6dd19aea1 --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9rlek/led.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <status_led.h> +#include <asm/arch/at91sam9rl.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> + +void coloured_LED_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOD); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); +} diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/Kconfig b/roms/u-boot/board/atmel/at91sam9x5ek/Kconfig new file mode 100644 index 000000000..3f92754fb --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9x5ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AT91SAM9X5EK + +config SYS_BOARD + default "at91sam9x5ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "at91sam9x5ek" + +endif diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9x5ek/MAINTAINERS new file mode 100644 index 000000000..51d2237ee --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9x5ek/MAINTAINERS @@ -0,0 +1,9 @@ +AT91SAM9X5EK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/at91sam9x5ek/ +F: include/configs/at91sam9x5ek.h +F: configs/at91sam9x5ek_dataflash_defconfig +F: configs/at91sam9x5ek_mmc_defconfig +F: configs/at91sam9x5ek_nandflash_defconfig +F: configs/at91sam9x5ek_spiflash_defconfig diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/Makefile b/roms/u-boot/board/atmel/at91sam9x5ek/Makefile new file mode 100644 index 000000000..e50948a5b --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9x5ek/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2012 +# Bo Shen <voice.shen@atmel.com> +# Atmel corporation <www.atmel.com> + +obj-y += at91sam9x5ek.o diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/roms/u-boot/board/atmel/at91sam9x5ek/at91sam9x5ek.c new file mode 100644 index 000000000..e0abe4aeb --- /dev/null +++ b/roms/u-boot/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Atmel Corporation + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <debug_uart.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +void at91_prepare_cpu_var(void); + +#ifdef CONFIG_CMD_NAND +static void at91sam9x5ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + /* NAND flash on D16 */ + csa |= AT91_MATRIX_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOCD); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + at91_prepare_cpu_var(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* arch number of AT91SAM9X5EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + at91sam9x5ek_nand_hw_init(); +#endif + +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD) + at91_uhp_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + at91_mci_hw_init(); +#elif CONFIG_NAND_BOOT + at91sam9x5ek_nand_hw_init(); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddrc_config ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(AT91_PMC_DDR, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); +} +#endif diff --git a/roms/u-boot/board/atmel/common/Makefile b/roms/u-boot/board/atmel/common/Makefile new file mode 100644 index 000000000..6bc8cabb8 --- /dev/null +++ b/roms/u-boot/board/atmel/common/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Microchip +# Wenyou Yang <wenyou.yang@microchip.com> + +obj-y += board.o +obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o +obj-$(CONFIG_SPI_FLASH_SFDP_SUPPORT) += mac-spi-nor.o +obj-$(CONFIG_DM_VIDEO) += video_display.o diff --git a/roms/u-boot/board/atmel/common/board.c b/roms/u-boot/board/atmel/common/board.c new file mode 100644 index 000000000..eee5c357b --- /dev/null +++ b/roms/u-boot/board/atmel/common/board.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Microchip + * Wenyou Yang <wenyou.yang@microchip.com> + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <w1.h> +#include <w1-eeprom.h> +#include <dm/device-internal.h> + +#define AT91_PDA_EEPROM_ID_OFFSET 15 +#define AT91_PDA_EEPROM_ID_LENGTH 5 +#define AT91_PDA_EEPROM_DEFAULT_BUS 0 + +char *get_cpu_name(void); + +void dummy(void) +{ +} + +#if defined CONFIG_W1 +void at91_pda_detect(void) +{ + struct udevice *bus, *dev; + u8 buf[AT91_PDA_EEPROM_ID_LENGTH + 1] = {0}; + int ret; + int pda = 0; + + ret = w1_get_bus(AT91_PDA_EEPROM_DEFAULT_BUS, &bus); + if (ret) + goto pda_detect_err; + + for (device_find_first_child(bus, &dev); + dev; + device_find_next_child(&dev)) { + ret = device_probe(dev); + if (ret) { + continue; + } else { + ret = w1_eeprom_read_buf(dev, AT91_PDA_EEPROM_ID_OFFSET, + (u8 *)buf, AT91_PDA_EEPROM_ID_LENGTH); + if (ret) + goto pda_detect_err; + break; + } + } + pda = simple_strtoul((const char *)buf, NULL, 10); + + switch (pda) { + case 7000: + if (buf[4] == 'B') + printf("PDA TM7000B detected\n"); + else + printf("PDA TM7000 detected\n"); + break; + case 4300: + printf("PDA TM4300 detected\n"); + break; + case 5000: + printf("PDA TM5000 detected\n"); + break; + } + +pda_detect_err: + env_set("pda", (const char *)buf); +} +#else +void at91_pda_detect(void) +{ +} +#endif + +void at91_prepare_cpu_var(void) +{ + env_set("cpu", get_cpu_name()); +} diff --git a/roms/u-boot/board/atmel/common/mac-spi-nor.c b/roms/u-boot/board/atmel/common/mac-spi-nor.c new file mode 100644 index 000000000..ced27b65e --- /dev/null +++ b/roms/u-boot/board/atmel/common/mac-spi-nor.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Tudor Ambarus <tudor.ambarus@microchip.com> + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <net.h> +#include <linux/mtd/spi-nor.h> +#include <netdev.h> + +#define ETH_ADDR_SIZE 6 + +#ifdef CONFIG_SPI_FLASH_SST +#define SFDP_MICROCHIP_MANUF_ID 0xbf +#define SFDP_MICROCHIP_MEM_TYPE 0x26 +#define SFDP_MICROCHIP_DEV_ID 0x43 + +#define SFDP_MICROCHIP_EUI_OFFSET 0x60 +#define SFDP_MICROCHIP_EUI48 0x30 + +struct sst26vf064beui { + u8 manufacturer_id; + u8 memory_type; + u8 device_id; + u8 reserved; +}; + +/** + * sst26vf064beui_check() - Check the validity of the EUI-48 information from + * the sst26vf064beui SPI NOR Microchip SFDP table. + * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP + * table. + * + * Return: 0 on success, -errno otherwise. + */ +static int sst26vf064beui_check(const u8 *manufacturer_sfdp) +{ + struct sst26vf064beui *sst26vf064beui = + (struct sst26vf064beui *)manufacturer_sfdp; + + if (sst26vf064beui->manufacturer_id != SFDP_MICROCHIP_MANUF_ID) + return -EINVAL; + + if (sst26vf064beui->memory_type != SFDP_MICROCHIP_MEM_TYPE) + return -EINVAL; + + if (sst26vf064beui->device_id != SFDP_MICROCHIP_DEV_ID) + return -EINVAL; + + /* + * Check if the EUI-48 MAC address is programmed in the next six address + * locations. + */ + if (manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET] != + SFDP_MICROCHIP_EUI48) + return -EINVAL; + + return 0; +} + +/** + * sst26vf064beui_get_ethaddr() - Get the ethernet address from the + * sst26vf064beui SPI NOR Microchip SFDP table. + * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP + * table. + * @ethaddr: pointer where to fill the ethernet address + * @size: size of the ethernet address. + * + * Return: 0 on success, -errno otherwise. + */ +static int sst26vf064beui_get_ethaddr(const u8 *manufacturer_sfdp, + u8 *ethaddr, size_t size) +{ + u64 eui_table[2]; + u64 *p = (u64 *)&manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET]; + int i, ret; + + ret = sst26vf064beui_check(manufacturer_sfdp); + if (ret) + return ret; + + for (i = 0; i < 2; i++) + eui_table[i] = le64_to_cpu(p[i]); + + /* Ethaddr starts at offset one. */ + memcpy(ethaddr, &((u8 *)eui_table)[1], size); + + return 0; +} +#endif + +/** + * at91_spi_nor_set_ethaddr() - Retrieve and set the ethernet address from the + * SPI NOR manufacturer specific SFDP table. + */ +void at91_spi_nor_set_ethaddr(void) +{ + struct udevice *dev; + struct spi_nor *nor; + const char *ethaddr_name = "ethaddr"; + u8 ethaddr[ETH_ADDR_SIZE] = {0}; + + if (env_get(ethaddr_name)) + return; + + if (uclass_first_device_err(UCLASS_SPI_FLASH, &dev)) + return; + + nor = dev_get_uclass_priv(dev); + if (!nor) + return; + + if (!nor->manufacturer_sfdp) + return; + +#ifdef CONFIG_SPI_FLASH_SST + if (sst26vf064beui_get_ethaddr(nor->manufacturer_sfdp, ethaddr, + ETH_ADDR_SIZE)) + return; +#endif + + if (is_valid_ethaddr(ethaddr)) + eth_env_set_enetaddr(ethaddr_name, ethaddr); +} diff --git a/roms/u-boot/board/atmel/common/mac_eeprom.c b/roms/u-boot/board/atmel/common/mac_eeprom.c new file mode 100644 index 000000000..a723ba723 --- /dev/null +++ b/roms/u-boot/board/atmel/common/mac_eeprom.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Microchip + * Wenyou Yang <wenyou.yang@microchip.com> + */ + +#include <common.h> +#include <dm.h> +#include <eeprom.h> +#include <env.h> +#include <i2c_eeprom.h> +#include <net.h> +#include <netdev.h> + +int at91_set_ethaddr(int offset) +{ + const int ETH_ADDR_LEN = 6; + unsigned char ethaddr[ETH_ADDR_LEN]; + const char *ETHADDR_NAME = "ethaddr"; + struct udevice *dev; + int ret; + + if (env_get(ETHADDR_NAME)) + return 0; + + ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, offset, ethaddr, 6); + if (ret) + return ret; + + if (is_valid_ethaddr(ethaddr)) + eth_env_set_enetaddr(ETHADDR_NAME, ethaddr); + + return 0; +} + +/* this function will set eth1addr from a second eeprom, if available */ +int at91_set_eth1addr(int offset) +{ + const int ETH_ADDR_LEN = 6; + unsigned char ethaddr[ETH_ADDR_LEN]; + /* configure eth1addr for second interface */ + const char *ETHADDR_NAME = "eth1addr"; + struct udevice *dev; + int ret; + + if (env_get(ETHADDR_NAME)) + return 0; + + /* first eeprom is retrieved, this is for the first interface */ + ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev); + if (ret) + return ret; + + /* attempt to obtain a second eeprom device */ + ret = uclass_next_device(&dev); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, offset, ethaddr, 6); + if (ret) + return ret; + + if (is_valid_ethaddr(ethaddr)) + eth_env_set_enetaddr(ETHADDR_NAME, ethaddr); + + return 0; +} diff --git a/roms/u-boot/board/atmel/common/video_display.c b/roms/u-boot/board/atmel/common/video_display.c new file mode 100644 index 000000000..a5049f4aa --- /dev/null +++ b/roms/u-boot/board/atmel/common/video_display.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Microchip + * Wenyou Yang <wenyou.yang@microchip.com> + */ + +#include <common.h> +#include <atmel_lcd.h> +#include <dm.h> +#include <init.h> +#include <nand.h> +#include <version.h> +#include <video.h> +#include <video_console.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int at91_video_show_board_info(void) +{ + struct vidconsole_priv *priv; + ulong dram_size, nand_size; + int i; + u32 len = 0; + char buf[255]; + char *corp = "Microchip Technology Inc.\n"; + char temp[32]; + struct udevice *dev, *con; + const char *s; + vidinfo_t logo_info; + int ret; + + len += sprintf(&buf[len], "%s\n", U_BOOT_VERSION); + memcpy(&buf[len], corp, strlen(corp)); + len += strlen(corp); + len += sprintf(&buf[len], "%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; +#ifdef CONFIG_NAND_ATMEL + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += get_nand_dev_by_index(i)->size; +#endif + + len += sprintf(&buf[len], "%ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, nand_size >> 20); + + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; + + microchip_logo_info(&logo_info); + ret = video_bmp_display(dev, logo_info.logo_addr, + logo_info.logo_x_offset, + logo_info.logo_y_offset, false); + if (ret) + return ret; + + ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con); + if (ret) + return ret; + + priv = dev_get_uclass_priv(con); + vidconsole_position_cursor(con, 0, (logo_info.logo_height + + priv->y_charsize - 1) / priv->y_charsize); + for (s = buf, i = 0; i < len; s++, i++) + vidconsole_put_char(con, *s); + + return 0; +} diff --git a/roms/u-boot/board/atmel/sam9x60ek/Kconfig b/roms/u-boot/board/atmel/sam9x60ek/Kconfig new file mode 100644 index 000000000..32fae2108 --- /dev/null +++ b/roms/u-boot/board/atmel/sam9x60ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAM9X60EK + +config SYS_BOARD + default "sam9x60ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "sam9x60ek" + +endif diff --git a/roms/u-boot/board/atmel/sam9x60ek/MAINTAINERS b/roms/u-boot/board/atmel/sam9x60ek/MAINTAINERS new file mode 100644 index 000000000..d209249c2 --- /dev/null +++ b/roms/u-boot/board/atmel/sam9x60ek/MAINTAINERS @@ -0,0 +1,9 @@ +SAM9X60EK BOARD +M: Sandeep Sheriker M <sandeep.sheriker@microchip.com> +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sam9x60ek/ +F: include/configs/sam9x60ek.h +F: configs/sam9x60ek_mmc_defconfig +F: configs/sam9x60ek_nandflash_defconfig +F: configs/sam9x60ek_qspiflash_defconfig diff --git a/roms/u-boot/board/atmel/sam9x60ek/Makefile b/roms/u-boot/board/atmel/sam9x60ek/Makefile new file mode 100644 index 000000000..12a406a3b --- /dev/null +++ b/roms/u-boot/board/atmel/sam9x60ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries +# +# Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com> + +obj-y += sam9x60ek.o diff --git a/roms/u-boot/board/atmel/sam9x60ek/sam9x60ek.c b/roms/u-boot/board/atmel/sam9x60ek/sam9x60ek.c new file mode 100644 index 000000000..32e5a2bf2 --- /dev/null +++ b/roms/u-boot/board/atmel/sam9x60ek/sam9x60ek.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_sfr.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <debug_uart.h> +#include <asm/mach-types.h> + +extern void at91_pda_detect(void); + +DECLARE_GLOBAL_DATA_PTR; + +void at91_prepare_cpu_var(void); + +#ifdef CONFIG_CMD_NAND +static void sam9x60ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + unsigned int csa; + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); + + at91_periph_clk_enable(ATMEL_ID_PIOD); + + /* Enable CS3 */ + csa = readl(&sfr->ebicsa); + csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60; + + writel(csa, &sfr->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) | + AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15), + &smc->cs[3].mode); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_prepare_cpu_var(); + + at91_pda_detect(); + + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +#define MAC24AA_MAC_OFFSET 0xfa + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + sam9x60ek_nand_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/Kconfig b/roms/u-boot/board/atmel/sama5d27_som1_ek/Kconfig new file mode 100644 index 000000000..3276214d8 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D27_SOM1_EK + +config SYS_BOARD + default "sama5d27_som1_ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d27_som1_ek" + +endif diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d27_som1_ek/MAINTAINERS new file mode 100644 index 000000000..ba2f31e6c --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -0,0 +1,14 @@ +SAMA5D27 SOM1 EK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d27_som1_ek/ +F: include/configs/sama5d27_som1_ek.h +F: configs/sama5d27_som1_ek_mmc_defconfig +F: configs/sama5d27_som1_ek_mmc1_defconfig +F: configs/sama5d27_som1_ek_qspiflash_defconfig + +SAMA5D27 GIANT BOARD +M: Greg Gallagher <greg@embeddedgreg.com> +S: Maintained +F: configs/sama5d27_giantboard_defconfig +F: arch/arm/dts/at91-sama5d27_giantboard.dts diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/Makefile b/roms/u-boot/board/atmel/sama5d27_som1_ek/Makefile new file mode 100644 index 000000000..72d320b1a --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Microchip Corporation +# Wenyou Yang <wenyou.yang@microchip.com> + +obj-y += sama5d27_som1_ek.o diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/roms/u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c new file mode 100644 index 000000000..1b7d946b5 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Microchip Corporation + * Wenyou.Yang <wenyou.yang@microchip.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +extern void at91_pda_detect(void); + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_USB +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + at91_pda_detect(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart1_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ + + at91_periph_clk_enable(ATMEL_ID_UART1); +} + +void board_debug_uart_init(void) +{ + board_uart1_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define MAC24AA_MAC_OFFSET 0xfa + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} +#endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_ZQ_LONG | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x511; + + ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x3, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(40) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Kconfig b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Kconfig new file mode 100644 index 000000000..4b192b084 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D27_WLSOM1_EK + +config SYS_BOARD + default "sama5d27_wlsom1_ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d27_wlsom1_ek" + +endif diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS new file mode 100644 index 000000000..ff68cf01a --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D27 WLSOM1 EK BOARD +M: Nicolas Ferre <nicolas.ferre@microchip.com> +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d27_wlsom1_ek/ +F: include/configs/sama5d27_wlsom1_ek.h +F: configs/sama5d27_wlsom1_ek_mmc_defconfig +F: configs/sama5d27_wlsom1_ek_qspiflash_defconfig diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Makefile b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Makefile new file mode 100644 index 000000000..cf827ae5e --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +# +# Author: Nicolas Ferre <nicolas.ferre@microcihp.com> + +obj-y += sama5d27_wlsom1_ek.o diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c new file mode 100644 index 000000000..32d51bba7 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre <nicolas.ferre@microcihp.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +extern void at91_pda_detect(void); + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + at91_pda_detect(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_SPI_FLASH_SFDP_SUPPORT + at91_spi_nor_set_ethaddr(); +#endif + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD + +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 1); /* GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 0); /* BLUE */ +} + +#ifdef CONFIG_SD_BOOT +void spl_mmc_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} +#endif + +#ifdef CONFIG_QSPI_BOOT +void spl_qspi_init(void) +{ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 5, 0); /* SCK */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 6, 0); /* CS */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 7, 0); /* IO0 */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 8, 0); /* IO1 */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 9, 0); /* IO2 */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 10, 0); /* IO3 */ + + at91_periph_clk_enable(ATMEL_ID_QSPI1); +} +#endif + +void spl_board_init(void) +{ + board_leds_init(); +#ifdef CONFIG_SD_BOOT + spl_mmc_init(); +#endif +#ifdef CONFIG_QSPI_BOOT + spl_qspi_init(); +#endif +} + +void spl_display_print(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ZQ_SHORT | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3); + + /* + * The AD220032D average time between REFRESH commands (Trefi): 3.9us + * 3.9us * 164MHz = 639.6 = 0x27F. + */ + ddrc->rtr = 0x27f; + /* Enable Adjust Refresh Rate */ + ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF; + + ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); + + ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15); + + /* + * According to the sama5d2 datasheet and the following values: + * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s + * Warning: note that the values T driftrate and V driftrate are dependent on + * the application environment. + * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s + * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize + * this timer to 0xFFFE. + */ + ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE); + + /* + * MR4 Read interval is dependent on the application environment. + * Here, we want to maximize this value as temperature is supposed + * to vary slowly in the application chosen. + * If Trefi is 3.9us, we have: + * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads. + */ + ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + ddrc_conf(&ddrc_config); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(40) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d2_icp/Kconfig b/roms/u-boot/board/atmel/sama5d2_icp/Kconfig new file mode 100644 index 000000000..385984551 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_icp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_ICP + +config SYS_BOARD + default "sama5d2_icp" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_icp" + +endif diff --git a/roms/u-boot/board/atmel/sama5d2_icp/MAINTAINERS b/roms/u-boot/board/atmel/sama5d2_icp/MAINTAINERS new file mode 100644 index 000000000..db984b6ae --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_icp/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 ICP BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d2_icp/ +F: include/configs/sama5d2_icp.h +F: configs/sama5d2_icp_mmc_defconfig + diff --git a/roms/u-boot/board/atmel/sama5d2_icp/Makefile b/roms/u-boot/board/atmel/sama5d2_icp/Makefile new file mode 100644 index 000000000..fd7e87059 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_icp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Microchip Technology Inc. +# Eugen Hristev <eugen.hristev@microchip.com> +# + +obj-y += sama5d2_icp.o diff --git a/roms/u-boot/board/atmel/sama5d2_icp/sama5d2_icp.c b/roms/u-boot/board/atmel/sama5d2_icp/sama5d2_icp.c new file mode 100644 index 000000000..3f33fcfc4 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Microchip Technology, Inc. + * Eugen Hristev <eugen.hristev@microchip.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_late_init(void) +{ + return 0; +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define MAC24AA_MAC_OFFSET 0xfa + +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD + +/* must set PB25 low to enable the CAN transceivers */ +static void board_can_stdby_dis(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0); +} + +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */ +} + +/* deassert reset lines for external periph in case of warm reboot */ +static void board_reset_additional_periph(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */ +} + +static void board_start_additional_periph(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */ +} + +#ifdef CONFIG_SD_BOOT +void spl_mmc_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} +#endif + +void spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + spl_mmc_init(); +#endif + board_reset_additional_periph(); + board_can_stdby_dis(); + board_leds_init(); +} + +void spl_display_print(void) +{ +} + +void spl_board_prepare_for_boot(void) +{ + board_start_additional_periph(); +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x298; + + ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x5355, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/Kconfig b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Kconfig new file mode 100644 index 000000000..8b202d6cc --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_PTC_EK + +config SYS_BOARD + default "sama5d2_ptc_ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_ptc_ek" + +endif diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d2_ptc_ek/MAINTAINERS new file mode 100644 index 000000000..9f82d9a3d --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D2 PTC EK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +M: Ludovic Desroches <ludovic.desroches@microchip.com> +S: Maintained +F: board/atmel/sama5d2_ptc_ek/ +F: include/configs/sama5d2_ptc_ek.h +F: configs/sama5d2_ptc_ek_mmc_defconfig +F: configs/sama5d2_ptc_ek_nandflash_defconfig diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/Makefile b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Makefile new file mode 100644 index 000000000..22f466439 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Microchip Corporation +# Wenyou Yang <wenyou.yang@microchip.com> + +obj-y += sama5d2_ptc_ek.o diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/roms/u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c new file mode 100644 index 000000000..a6937e7d5 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Microchip Corporation + * Wenyou Yang <wenyou.yang@microchip.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <i2c.h> +#include <init.h> +#include <nand.h> +#include <version.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> +#include <asm/arch/sama5d2_smc.h> + +extern void at91_pda_detect(void); + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_NAND_ATMEL +static void board_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_HSMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) | + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME); /* D0 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME); /* D1 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME); /* D2 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME); /* D3 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME); /* D4 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME); /* D5 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME); /* D6 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME); /* D7 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK); /* NCS */ + atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK); /* RDY */ + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK); /* ALE */ + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK); /* CLE */ +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_pda_detect(); + return 0; +} +#endif + +#ifdef CONFIG_CMD_USB +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK); +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + board_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define AT24MAC_MAC_OFFSET 0xfa + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(AT24MAC_MAC_OFFSET); +#endif + return 0; +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/Kconfig b/roms/u-boot/board/atmel/sama5d2_xplained/Kconfig new file mode 100644 index 000000000..55712e974 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_xplained/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_XPLAINED + +config SYS_BOARD + default "sama5d2_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_xplained" + +endif diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/MAINTAINERS b/roms/u-boot/board/atmel/sama5d2_xplained/MAINTAINERS new file mode 100644 index 000000000..88e327f81 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_xplained/MAINTAINERS @@ -0,0 +1,9 @@ +SAMA5D2 XPLAINED BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d2_xplained/ +F: include/configs/sama5d2_xplained.h +F: configs/sama5d2_xplained_mmc_defconfig +F: configs/sama5d2_xplained_spiflash_defconfig +F: configs/sama5d2_xplained_emmc_defconfig +F: configs/sama5d2_xplained_qspiflash_defconfig diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/Makefile b/roms/u-boot/board/atmel/sama5d2_xplained/Makefile new file mode 100644 index 000000000..39ba24d5f --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_xplained/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Atmel Corporation +# Wenyou Yang <wenyou.yang@atmel.com> + +obj-y += sama5d2_xplained.o diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/roms/u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c new file mode 100644 index 000000000..5110ec896 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +extern void at91_pda_detect(void); + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_USB +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + at91_pda_detect(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart1_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ + + at91_periph_clk_enable(ATMEL_ID_UART1); +} + +void board_debug_uart_init(void) +{ + board_uart1_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define AT24MAC_MAC_OFFSET 0x9a + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(AT24MAC_MAC_OFFSET); +#endif + + return 0; +} +#endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DIS_DLL | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x511; + + ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | + 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET); + + ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x3, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x0 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/Kconfig b/roms/u-boot/board/atmel/sama5d3_xplained/Kconfig new file mode 100644 index 000000000..2df751a26 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3_xplained/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAMA5D3_XPLAINED + +config SYS_BOARD + default "sama5d3_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "sama5d3_xplained" + +endif diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/MAINTAINERS b/roms/u-boot/board/atmel/sama5d3_xplained/MAINTAINERS new file mode 100644 index 000000000..69b4ee8a3 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3_xplained/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D3_XPLAINED BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d3_xplained/ +F: include/configs/sama5d3_xplained.h +F: configs/sama5d3_xplained_mmc_defconfig +F: configs/sama5d3_xplained_nandflash_defconfig diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/Makefile b/roms/u-boot/board/atmel/sama5d3_xplained/Makefile new file mode 100644 index 000000000..b6bcd3c0a --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3_xplained/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2014 +# Bo Shen <voice.shen@atmel.com> + +obj-y += sama5d3_xplained.o diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/roms/u-boot/board/atmel/sama5d3_xplained/sama5d3_xplained.c new file mode 100644 index 000000000..db9603f58 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <debug_uart.h> +#include <spl.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/at91_wdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void at91_pda_detect(void); + +#ifdef CONFIG_NAND_ATMEL +void sama5d3_xplained_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | + AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | + AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d3_xplained_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 3, 0); + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +static void sama5d3_xplained_mci0_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_pda_detect(); + return 0; +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + sama5d3_xplained_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d3_xplained_usb_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d3_xplained_mci0_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d3_xplained_mci0_hw_init(); +#endif +#elif CONFIG_NAND_BOOT + sama5d3_xplained_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ENRDM_ON | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + /* + * As the DDR2-SDRAm device requires a refresh time is 7.8125us + * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks + */ + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct atmel_mpddrc_config ddr2; + + ddr2_conf(&ddr2); + + /* Enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); + + tmp = AT91_PMC_MCKR_MDIV_4 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d3xek/Kconfig b/roms/u-boot/board/atmel/sama5d3xek/Kconfig new file mode 100644 index 000000000..abd1ad81f --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3xek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAMA5D3XEK + +config SYS_BOARD + default "sama5d3xek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "sama5d3xek" + +endif diff --git a/roms/u-boot/board/atmel/sama5d3xek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d3xek/MAINTAINERS new file mode 100644 index 000000000..e8ec275d7 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3xek/MAINTAINERS @@ -0,0 +1,11 @@ +SAMA5D3XEK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d3xek/ +F: include/configs/sama5d3xek.h +F: configs/sama5d3xek_mmc_defconfig +F: configs/sama5d3xek_nandflash_defconfig +F: configs/sama5d3xek_spiflash_defconfig +F: configs/sama5d36ek_cmp_mmc_defconfig +F: configs/sama5d36ek_cmp_nandflash_defconfig +F: configs/sama5d36ek_cmp_spiflash_defconfig diff --git a/roms/u-boot/board/atmel/sama5d3xek/Makefile b/roms/u-boot/board/atmel/sama5d3xek/Makefile new file mode 100644 index 000000000..6fe1b13b0 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3xek/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2013 +# Bo Shen <voice.shen@atmel.com> + +obj-y += sama5d3xek.o diff --git a/roms/u-boot/board/atmel/sama5d3xek/sama5d3xek.c b/roms/u-boot/board/atmel/sama5d3xek/sama5d3xek.c new file mode 100644 index 000000000..b6f8dcd91 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d3xek/sama5d3xek.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 - 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <debug_uart.h> +#include <env.h> +#include <linux/ctype.h> +#include <spl.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/at91_wdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_NAND_ATMEL +void sama5d3xek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | + AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | + AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); +} +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +static void sama5d3xek_nor_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS0 for NOR flash */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[0].setup); + writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) | + AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11), + &smc->cs[0].pulse); + writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14), + &smc->cs[0].cycle); + writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) | + AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) | + AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)| + AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[0].mode); + + /* Address pin (A1 ~ A23) configuration */ + at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0); + /* CS0 pin configuration */ + at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0); +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d3xek_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTD, 25, 0); + at91_set_pio_output(AT91_PIO_PORTD, 26, 0); + at91_set_pio_output(AT91_PIO_PORTD, 27, 0); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +static void sama5d3xek_mci_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */ +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + sama5d3xek_nand_hw_init(); +#endif +#ifdef CONFIG_MTD_NOR_FLASH + sama5d3xek_nor_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d3xek_usb_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d3xek_mci_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + const int MAX_STR_LEN = 32; + char name[MAX_STR_LEN], *p; + int i; + + strncpy(name, get_cpu_name(), MAX_STR_LEN); + for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++) + *p = tolower(*p); + + strcat(name, "ek.dtb"); + env_set("dtb_name", name); +#endif +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + return 0; +} +#endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#if CONFIG_NAND_BOOT + sama5d3xek_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ENRDM_ON | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + /* + * As the DDR2-SDRAm device requires a refresh time is 7.8125us + * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks + */ + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct atmel_mpddrc_config ddr2; + + ddr2_conf(&ddr2); + + /* Enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); + + tmp = AT91_PMC_MCKR_MDIV_4 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/Kconfig b/roms/u-boot/board/atmel/sama5d4_xplained/Kconfig new file mode 100644 index 000000000..2cb03cb17 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4_xplained/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAMA5D4_XPLAINED + +config SYS_BOARD + default "sama5d4_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "sama5d4_xplained" + +endif diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/MAINTAINERS b/roms/u-boot/board/atmel/sama5d4_xplained/MAINTAINERS new file mode 100644 index 000000000..9fd0ad7bc --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4_xplained/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D4 XPLAINED ULTRA BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d4_xplained/ +F: include/configs/sama5d4_xplained.h +F: configs/sama5d4_xplained_mmc_defconfig +F: configs/sama5d4_xplained_nandflash_defconfig +F: configs/sama5d4_xplained_spiflash_defconfig diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/Makefile b/roms/u-boot/board/atmel/sama5d4_xplained/Makefile new file mode 100644 index 000000000..a79a97420 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4_xplained/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2014 Atmel +# Bo Shen <voice.shen@atmel.com> + +obj-y += sama5d4_xplained.o diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/roms/u-boot/board/atmel/sama5d4_xplained/sama5d4_xplained.c new file mode 100644 index 000000000..2088b48b7 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/sama5d4.h> +#include <debug_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void at91_pda_detect(void); + +#ifdef CONFIG_NAND_ATMEL +static void sama5d4_xplained_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d4_xplained_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 1); + at91_set_pio_output(AT91_PIO_PORTE, 14, 1); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_pda_detect(); +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void sama5d4_xplained_serial3_hw_init(void) +{ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +void board_debug_uart_init(void) +{ + sama5d4_xplained_serial3_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +#define AT24MAC_MAC_OFFSET 0x9a + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(AT24MAC_MAC_OFFSET); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + sama5d4_xplained_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d4_xplained_usb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#if CONFIG_NAND_BOOT + sama5d4_xplained_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddr2->rtr = 0x2b0; + + ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct atmel_mpddrc_config ddr2; + + ddr2_conf(&ddr2); + + /* Enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(87) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama5d4ek/Kconfig b/roms/u-boot/board/atmel/sama5d4ek/Kconfig new file mode 100644 index 000000000..1a634032a --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAMA5D4EK + +config SYS_BOARD + default "sama5d4ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "sama5d4ek" + +endif diff --git a/roms/u-boot/board/atmel/sama5d4ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d4ek/MAINTAINERS new file mode 100644 index 000000000..f715af640 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4ek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D4EK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama5d4ek/ +F: include/configs/sama5d4ek.h +F: configs/sama5d4ek_mmc_defconfig +F: configs/sama5d4ek_nandflash_defconfig +F: configs/sama5d4ek_spiflash_defconfig diff --git a/roms/u-boot/board/atmel/sama5d4ek/Makefile b/roms/u-boot/board/atmel/sama5d4ek/Makefile new file mode 100644 index 000000000..b5696c8c0 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4ek/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2014 Atmel +# Bo Shen <voice.shen@atmel.com> + +obj-y += sama5d4ek.o diff --git a/roms/u-boot/board/atmel/sama5d4ek/sama5d4ek.c b/roms/u-boot/board/atmel/sama5d4ek/sama5d4ek.c new file mode 100644 index 000000000..46ec1eb32 --- /dev/null +++ b/roms/u-boot/board/atmel/sama5d4ek/sama5d4ek.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/sama5d4.h> +#include <debug_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_NAND_ATMEL +static void sama5d4ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d4ek_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 0); + at91_set_pio_output(AT91_PIO_PORTE, 12, 0); + at91_set_pio_output(AT91_PIO_PORTE, 10, 0); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void sama5d4ek_serial3_hw_init(void) +{ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +void board_debug_uart_init(void) +{ + sama5d4ek_serial3_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + sama5d4ek_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d4ek_usb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#if CONFIG_NAND_BOOT + sama5d4ek_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddr2->rtr = 0x2b0; + + ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct atmel_mpddrc_config ddr2; + const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + u32 tmp; + + ddr2_conf(&ddr2); + + /* Enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE; + writel(tmp, &mpddr->rd_data_path); + + tmp = readl(&mpddr->io_calibr); + tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV | + ATMEL_MPDDRC_IO_CALIBR_TZQIO | + ATMEL_MPDDRC_IO_CALIBR_CALCODEP | + ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) | + ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 | + ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) | + ATMEL_MPDDRC_IO_CALIBR_EN_CALIB; + writel(tmp, &mpddr->io_calibr); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(87) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/roms/u-boot/board/atmel/sama7g5ek/Kconfig b/roms/u-boot/board/atmel/sama7g5ek/Kconfig new file mode 100644 index 000000000..a89db8d8a --- /dev/null +++ b/roms/u-boot/board/atmel/sama7g5ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA7G5EK + +config SYS_BOARD + default "sama7g5ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama7g5ek" + +endif diff --git a/roms/u-boot/board/atmel/sama7g5ek/MAINTAINERS b/roms/u-boot/board/atmel/sama7g5ek/MAINTAINERS new file mode 100644 index 000000000..eac972968 --- /dev/null +++ b/roms/u-boot/board/atmel/sama7g5ek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA7G5 EK BOARD +M: Eugen Hristev <eugen.hristev@microchip.com> +S: Maintained +F: board/atmel/sama7g5ek.c +F: include/configs/sama7g5ek.h +F: configs/sama7g5ek_mmc1_defconfig +F: configs/sama7g5ek_mmc_defconfig + diff --git a/roms/u-boot/board/atmel/sama7g5ek/Makefile b/roms/u-boot/board/atmel/sama7g5ek/Makefile new file mode 100644 index 000000000..a6eedd10f --- /dev/null +++ b/roms/u-boot/board/atmel/sama7g5ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Microchip Technology Inc. +# Eugen Hristev <eugen.hristev@microchip.com> +# + +obj-y += sama7g5ek.o diff --git a/roms/u-boot/board/atmel/sama7g5ek/sama7g5ek.c b/roms/u-boot/board/atmel/sama7g5ek/sama7g5ek.c new file mode 100644 index 000000000..4df43d81f --- /dev/null +++ b/roms/u-boot/board/atmel/sama7g5ek/sama7g5ek.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology, Inc. + * Eugen Hristev <eugen.hristev@microchip.com> + */ + +#include <common.h> +#include <debug_uart.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama7g5.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_late_init(void) +{ + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_uart0_hw_init(void) +{ + /* FLEXCOM3 IO0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTD, 17, ATMEL_PIO_PUEN_MASK); + /* FLEXCOM3 IO1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTD, 16, 0); + + at91_periph_clk_enable(ATMEL_ID_FLEXCOM3); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ +#if (IS_ENABLED(CONFIG_DEBUG_UART)) + debug_uart_init(); +#endif + return 0; +} + +#define MAC24AA_MAC_OFFSET 0xfa + +#if (IS_ENABLED(CONFIG_MISC_INIT_R)) +int misc_init_r(void) +{ +#if (IS_ENABLED(CONFIG_I2C_EEPROM)) + at91_set_ethaddr(MAC24AA_MAC_OFFSET); + at91_set_eth1addr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + |