diff options
Diffstat (limited to 'roms/u-boot/board/keymile/km83xx')
| -rw-r--r-- | roms/u-boot/board/keymile/km83xx/Kconfig | 176 | ||||
| -rw-r--r-- | roms/u-boot/board/keymile/km83xx/MAINTAINERS | 31 | ||||
| -rw-r--r-- | roms/u-boot/board/keymile/km83xx/Makefile | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/keymile/km83xx/README.kmeter1 | 91 | ||||
| -rw-r--r-- | roms/u-boot/board/keymile/km83xx/km83xx.c | 246 | ||||
| -rw-r--r-- | roms/u-boot/board/keymile/km83xx/km83xx_i2c.c | 73 |
6 files changed, 623 insertions, 0 deletions
diff --git a/roms/u-boot/board/keymile/km83xx/Kconfig b/roms/u-boot/board/keymile/km83xx/Kconfig new file mode 100644 index 000000000..8247ae39d --- /dev/null +++ b/roms/u-boot/board/keymile/km83xx/Kconfig @@ -0,0 +1,176 @@ +menu "KM 83xx Options" + depends on MPC83xx + +config KM_ENABLE_FULL_DM_DTS_SUPPORT + bool "enable full DM/DTS support for KM 83xx boards" + default y + select CMD_DM + select DM + select DM_ETH + select DM_MDIO + select DM_SERIAL + select OF_CONTROL + select PINCTRL + select PINCTRL_QE + select PHYLIB +endmenu + +config SYS_MEMTEST_START + default 0x00100000 + +config SYS_MEMTEST_END + default 0x00f00000 + +if TARGET_KMETER1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmeter1" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC8360 + imply CMD_CRAMFS + imply CMD_DIAG + imply FS_CRAMFS + +endif + +if TARGET_KMCOGE5NE + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmcoge5ne" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC8360 + imply CMD_CRAMFS + imply CMD_DIAG + imply FS_CRAMFS + +endif + +if TARGET_KMTEGR1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtegr1" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC8309 + imply CMD_CRAMFS + imply FS_CRAMFS + +endif + +if TARGET_TUXX1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "tuxx1" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +endif + +if TARGET_KMSUPX5 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmsupx5" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +endif + +if TARGET_TUGE1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "tuge1" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +endif + +if TARGET_KMOPTI2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmopti2" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +endif + +if TARGET_KMTEPR2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtepr2" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +endif diff --git a/roms/u-boot/board/keymile/km83xx/MAINTAINERS b/roms/u-boot/board/keymile/km83xx/MAINTAINERS new file mode 100644 index 000000000..9268719a7 --- /dev/null +++ b/roms/u-boot/board/keymile/km83xx/MAINTAINERS @@ -0,0 +1,31 @@ +KM83XX BOARD +M: Holger Brunck <holger.brunck@hitachi-powergrids.com> +M: Heiko Schocher <hs@denx.de> +S: Maintained +F: board/keymile/km83xx/ +F: include/configs/km8360.h +F: configs/kmcoge5ne_defconfig +F: configs/kmeter1_defconfig +F: include/configs/tuxx1.h +F: configs/kmopti2_defconfig +F: configs/kmsupx5_defconfig +F: configs/kmtepr2_defconfig +F: configs/kmtegr1_defconfig +F: configs/tuge1_defconfig +F: configs/tuxx1_defconfig +F: arch/powerpc/dts/km8309-uboot.dtsi +F: arch/powerpc/dts/km8321-uboot.dtsi +F: arch/powerpc/dts/km8321.dtsi +F: arch/powerpc/dts/km836x-uboot.dtsi +F: arch/powerpc/dts/km836x.dtsi +F: arch/powerpc/dts/kmcoge5ne-uboot.dtsi +F: arch/powerpc/dts/kmcoge5ne.dts +F: arch/powerpc/dts/kmeter1-uboot.dtsi +F: arch/powerpc/dts/kmeter1.dts +F: arch/powerpc/dts/kmopti2.dts +F: arch/powerpc/dts/kmsupc5.dts +F: arch/powerpc/dts/kmsupm5.dts +F: arch/powerpc/dts/kmtegr1.dts +F: arch/powerpc/dts/kmtepr2.dts +F: arch/powerpc/dts/kmtuge1.dts +F: arch/powerpc/dts/kmtuxa1.dts diff --git a/roms/u-boot/board/keymile/km83xx/Makefile b/roms/u-boot/board/keymile/km83xx/Makefile new file mode 100644 index 000000000..0aef65498 --- /dev/null +++ b/roms/u-boot/board/keymile/km83xx/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o diff --git a/roms/u-boot/board/keymile/km83xx/README.kmeter1 b/roms/u-boot/board/keymile/km83xx/README.kmeter1 new file mode 100644 index 000000000..b85d7764b --- /dev/null +++ b/roms/u-boot/board/keymile/km83xx/README.kmeter1 @@ -0,0 +1,91 @@ +Keymile kmeter1 Board +----------------------------------------- +1. Alternative Boot EEPROM + + Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot + configuration from a serial EEPROM. During the development and debugging + phase it might be helpful to apply an alternative boot configuration in + a simple way. Therefore it is an alternative boot eeprom on the PIGGY, + which can be activated by setting the "ST" jumper on the PIGGY board. + +2. Memory Map + + BaseAddr PortSz Size Device + ----------- ------ ----- ------ + 0x0000_0000 64 bit 256MB DDR + 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 + 0xa000_0000 8 bit 256MB PAXE on CS3 + 0xe000_0000 2MB Int Mem Reg Space + 0xf000_0000 16 bit 256MB FLASH on CS0 + + + DDR-SDRAM: + The current realization is made with four 16-bits memory devices. + Mounting options have been foreseen for device architectures from + 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices + thus resulting in a total capacity of 256MBytes. + +3. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make kmeter1_config + make + +4. Downloading and Flashing Images + +4.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + => run load + Using UEC0 device + TFTP from server 192.168.1.1; our IP address is 192.168.205.4 + Filename '/tftpboot/kmeter1/u-boot.bin'. + Load address: 0x200000 + Loading: ############## + done + Bytes transferred = 204204 (31dac hex) + => + +4.1 Reflash U-Boot Image using U-Boot + + => run update + ..... done + Un-Protected 5 sectors + + ..... done + Erased 5 sectors + Copy to Flash... done + ..... done + Protected 5 sectors + Total of 204204 bytes were the same + Saving Environment to Flash... + . done + Un-Protected 1 sectors + . done + Un-Protected 1 sectors + Erasing Flash... + . done + Erased 1 sectors + Writing to Flash... done + . done + Protected 1 sectors + . done + Protected 1 sectors + => + +5. Notes + 1) The console baudrate for kmeter1 is 115200bps. diff --git a/roms/u-boot/board/keymile/km83xx/km83xx.c b/roms/u-boot/board/keymile/km83xx/km83xx.c new file mode 100644 index 000000000..ecc8c786b --- /dev/null +++ b/roms/u-boot/board/keymile/km83xx/km83xx.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada <peterb@logicpd.com> + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * (C) Copyright 2008 - 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#include <common.h> +#include <env.h> +#include <fdt_support.h> +#include <init.h> +#include <ioports.h> +#include <log.h> +#include <mpc83xx.h> +#include <i2c.h> +#include <miiphy.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <pci.h> +#include <linux/delay.h> +#include <linux/libfdt.h> +#include <post.h> + +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + +static int piggy_present(void) +{ + struct km_bec_fpga __iomem *base = + (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; + + return in_8(&base->bprth) & PIGGY_PRESENT; +} + +int ethernet_present(void) +{ + return piggy_present(); +} + +int board_early_init_r(void) +{ + struct km_bec_fpga *base = + (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + +#if defined(CONFIG_ARCH_MPC8360) + unsigned short svid; + /* + * Because of errata in the UCCs, we have to write to the reserved + * registers to slow the clocks down. + */ + svid = SVR_REV(mfspr(SVR)); + switch (svid) { + case 0x0020: + /* + * MPC8360ECE.pdf QE_ENET10 table 4: + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ + setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); + break; + case 0x0021: + /* + * MPC8360ECE.pdf QE_ENET10 table 4: + * IMMR + 0x14AC[24:27] = 1010 + */ + clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), + 0x00000050, 0x000000a0); + break; + } +#endif + + /* enable the PHY on the PIGGY */ + setbits_8(&base->pgy_eth, 0x01); + /* enable the Unit LED (green) */ + setbits_8(&base->oprth, WRL_BOOT); + /* enable Application Buffer */ + setbits_8(&base->oprtl, OPRTL_XBUFENA); + + return 0; +} + +int misc_init_r(void) +{ + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + CONFIG_PIGGY_MAC_ADDRESS_OFFSET); + return 0; +} + +int last_stage_init(void) +{ +#if defined(CONFIG_TARGET_KMCOGE5NE) + struct bfticu_iomap *base = + (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; + u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; + + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + env_set("actual_bank", "0"); + } +#endif + set_km_env(); + return 0; +} + +static int fixed_sdram(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); + out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + udelay(200); + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + + msize = CONFIG_SYS_DDR_SIZE << 20; + disable_addr_trans(); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); + enable_addr_trans(); + msize /= (1024 * 1024); + if (CONFIG_SYS_DDR_SIZE != msize) { + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size >> 1, ddr_size_log2++) + if (ddr_size & 1) + return -1; + out_be32(&im->sysconf.ddrlaw[0].ar, + (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); + out_be32(&im->ddr.csbnds[0].csbnds, + (((msize / 16) - 1) & 0xff)); + } + + return msize; +} + +int dram_init(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -ENXIO; + + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); + msize = fixed_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize DDR ECC byte + */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + gd->ram_size = msize * 1024 * 1024; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME); + + if (piggy_present()) + puts(" with PIGGY."); + puts("\n"); + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + + return 0; +} + +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var(void) +{ + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} +#endif + +#if defined(CONFIG_POST) +int post_hotkeys_pressed(void) +{ + int testpin = 0; + struct km_bec_fpga *base = + (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); + testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; + debug("post_hotkeys_pressed: %d\n", !testpin); + return testpin; +} + +ulong post_word_load(void) +{ + void* addr = (ulong *) (CPM_POST_WORD_ADDR); + debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr)); + return in_le32(addr); + +} +void post_word_store(ulong value) +{ + void* addr = (ulong *) (CPM_POST_WORD_ADDR); + debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value); + out_le32(addr, value); +} + +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + *vstart = CONFIG_SYS_MEMTEST_START; + *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; + debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); + + return 0; +} +#endif diff --git a/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c b/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c new file mode 100644 index 000000000..62100b194 --- /dev/null +++ b/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <linux/ctype.h> +#include <linux/delay.h> +#include "../common/common.h" + +static void i2c_write_start_seq(void) +{ + struct fsl_i2c_base *base; + base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + + CONFIG_SYS_I2C_OFFSET); + udelay(DELAY_ABORT_SEQ); + out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + out_8(&base->cr, (I2C_CR_MEN)); +} + +int i2c_make_abort(void) +{ + struct fsl_i2c_base *base; + base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + + CONFIG_SYS_I2C_OFFSET); + uchar last; + int nbr_read = 0; + int i = 0; + int ret = 0; + + /* wait after each operation to finsh with a delay */ + out_8(&base->cr, (I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + in_8(&base->dr); + udelay(DELAY_ABORT_SEQ); + last = in_8(&base->dr); + nbr_read++; + + /* + * do read until the last bit is 1, but stop if the full eeprom is + * read. + */ + while (((last & 0x01) != 0x01) && + (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) { + udelay(DELAY_ABORT_SEQ); + last = in_8(&base->dr); + nbr_read++; + } + if ((last & 0x01) != 0x01) + ret = -2; + if ((last != 0xff) || (nbr_read > 1)) + printf("[INFO] i2c abort after %d bytes (0x%02x)\n", + nbr_read, last); + udelay(DELAY_ABORT_SEQ); + out_8(&base->cr, (I2C_CR_MEN)); + udelay(DELAY_ABORT_SEQ); + /* clear status reg */ + out_8(&base->sr, 0); + + for (i = 0; i < 5; i++) + i2c_write_start_seq(); + if (ret != 0) + printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n", + nbr_read, last); + + return ret; +} |