4 files changed, 83 insertions, 0 deletions
diff --git a/roms/u-boot/board/qca/ap121/Kconfig b/roms/u-boot/board/qca/ap121/Kconfig
new file mode 100644
index 000000000..4fd6a7167
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/Kconfig
@@ -0,0 +1,27 @@
+if TARGET_AP121
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap121"
+
+config SYS_CONFIG_NAME
+	default "ap121"
+
+config SYS_TEXT_BASE
+	default 0x9f000000
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
+endif
diff --git a/roms/u-boot/board/qca/ap121/MAINTAINERS b/roms/u-boot/board/qca/ap121/MAINTAINERS
new file mode 100644
index 000000000..8b02988d6
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/MAINTAINERS
@@ -0,0 +1,6 @@
+AP121 BOARD
+M:	Wills Wang <wills.wang@live.com>
+S:	Maintained
+F:	board/qca/ap121/
+F:	include/configs/ap121.h
+F:	configs/ap121_defconfig
diff --git a/roms/u-boot/board/qca/ap121/Makefile b/roms/u-boot/board/qca/ap121/Makefile
new file mode 100644
index 000000000..7cdf53cf9
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	= ap121.o
diff --git a/roms/u-boot/board/qca/ap121/ap121.c b/roms/u-boot/board/qca/ap121/ap121.c
new file mode 100644
index 000000000..60a2e1914
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/ap121.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <mach/ath79.h>
+#include <debug_uart.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val &= ~AR933X_GPIO(9);
+	val |= AR933X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_FUNC);
+	val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
+	writel(val, regs + AR71XX_GPIO_REG_FUNC);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	ddr_init();
+	ath79_eth_reset();
+	return 0;
+}