diff options
Diffstat (limited to 'roms/u-boot/board/siemens')
41 files changed, 4961 insertions, 0 deletions
diff --git a/roms/u-boot/board/siemens/capricorn/Kconfig b/roms/u-boot/board/siemens/capricorn/Kconfig new file mode 100644 index 000000000..21c3ef909 --- /dev/null +++ b/roms/u-boot/board/siemens/capricorn/Kconfig @@ -0,0 +1,25 @@ +if TARGET_GIEDI + +config SYS_BOARD + default "capricorn" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "giedi" + +endif + +if TARGET_DENEB + +config SYS_BOARD + default "capricorn" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "deneb" + +endif diff --git a/roms/u-boot/board/siemens/capricorn/MAINTAINERS b/roms/u-boot/board/siemens/capricorn/MAINTAINERS new file mode 100644 index 000000000..bc7d163e1 --- /dev/null +++ b/roms/u-boot/board/siemens/capricorn/MAINTAINERS @@ -0,0 +1,11 @@ +CAPRICORN BOARD +M: Anatolij Gustschin <agust@denx.de> +S: Maintained +F: board/siemens/capricorn/ +F: include/configs/capricorn-common.h +F: include/configs/deneb.h +F: include/configs/giedi.h +F: include/configs/siemens-ccp-common.h +F: include/configs/siemens-env-common.h +F: configs/deneb_defconfig +F: configs/giedi_defconfig diff --git a/roms/u-boot/board/siemens/capricorn/Makefile b/roms/u-boot/board/siemens/capricorn/Makefile new file mode 100644 index 000000000..d5846cc8e --- /dev/null +++ b/roms/u-boot/board/siemens/capricorn/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Siemens AG +# + +obj-y += board.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += ../common/factoryset.o +endif diff --git a/roms/u-boot/board/siemens/capricorn/board.c b/roms/u-boot/board/siemens/capricorn/board.c new file mode 100644 index 000000000..dcbab8e4d --- /dev/null +++ b/roms/u-boot/board/siemens/capricorn/board.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + * + * Copyright 2019 Siemens AG + * + */ +#include <common.h> +#include <command.h> +#include <dm.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <log.h> +#include <netdev.h> +#include <env_internal.h> +#include <fsl_esdhc_imx.h> +#include <i2c.h> +#include <led.h> +#include <pca953x.h> +#include <power-domain.h> +#include <asm/gpio.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/sys_proto.h> +#ifndef CONFIG_SPL +#include <asm/arch-imx8/clock.h> +#endif +#include <linux/delay.h> +#include "../common/factoryset.h" + +#define GPIO_PAD_CTRL \ + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL \ + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL \ + ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart2_pads[] = { + SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +int board_early_init_f(void) +{ + /* Set UART clock root to 80 MHz */ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + ret |= sc_pm_setup_uart(SC_R_UART_2, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#define ENET_PHY_RESET IMX_GPIO_NR(0, 3) +#define ENET_TEST_1 IMX_GPIO_NR(0, 8) +#define ENET_TEST_2 IMX_GPIO_NR(0, 9) + +/*#define ETH_IO_TEST*/ +static iomux_cfg_t enet_reset[] = { + SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +#ifdef ETH_IO_TEST + /* GPIO0.IO08 MODE3: TXD0 */ + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) | + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + /* GPIO0.IO09 MODE3: TXD1 */ + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) | + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +#endif +}; + +static void enet_device_phy_reset(void) +{ + int ret = 0; + + imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset)); + + ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset"); + if (!ret) { + gpio_direction_output(ENET_PHY_RESET, 1); + gpio_set_value(ENET_PHY_RESET, 0); + /* SMSC9303 TRM chapter 14.5.2 */ + udelay(200); + gpio_set_value(ENET_PHY_RESET, 1); + } else { + printf("ENET RESET failed!\n"); + } + +#ifdef ETH_IO_TEST + ret = gpio_request(ENET_TEST_1, "enet_test1"); + if (!ret) { + int i; + + printf("ENET TEST 1!\n"); + for (i = 0; i < 20; i++) { + gpio_direction_output(ENET_TEST_1, 1); + gpio_set_value(ENET_TEST_1, 0); + udelay(50); + gpio_set_value(ENET_TEST_1, 1); + udelay(50); + } + gpio_free(ENET_TEST_1); + } else { + printf("GPIO for ENET TEST 1 failed!\n"); + } + ret = gpio_request(ENET_TEST_2, "enet_test2"); + if (!ret) { + int i; + + printf("ENET TEST 2!\n"); + for (i = 0; i < 20; i++) { + gpio_direction_output(ENET_TEST_2, 1); + gpio_set_value(ENET_TEST_2, 0); + udelay(50); + gpio_set_value(ENET_TEST_2, 1); + udelay(50); + } + gpio_free(ENET_TEST_2); + } else { + printf("GPIO for ENET TEST 2 failed!\n"); + } +#endif +} + +int setup_gpr_fec(void) +{ + sc_ipc_t ipc_handle = -1; + sc_err_t err = 0; + unsigned int test; + + /* + * TX_CLK_SEL: it controls a mux between clock coming from the pad 50M + * input pin and clock generated internally to connectivity subsystem + * 0: internal clock + * 1: external clock ---> your choice for RMII + * + * CLKDIV_SEL: it controls a div by 2 on the internal clock path à + * it should be don’t care when using external clock + * 0: non-divided clock + * 1: clock divided by 2 + * 50_DISABLE or 125_DISABLE: + * it’s used to disable the clock tree going outside the chip + * when reference clock is generated internally. + * It should be don’t care when reference clock is provided + * externally. + * 0: clock is enabled + * 1: clock is disabled + * + * SC_C_TXCLK = 24, + * SC_C_CLKDIV = 25, + * SC_C_DISABLE_50 = 26, + * SC_C_DISABLE_125 = 27, + */ + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#endif + +static int setup_fec(void) +{ + setup_gpr_fec(); + /* Reset ENET PHY */ + enet_device_phy_reset(); + return 0; +} + +void reset_cpu(void) +{ +} + +#ifndef CONFIG_SPL_BUILD +/* LED's */ +static int board_led_init(void) +{ + struct udevice *bus, *dev; + u8 pca_led[2] = { 0x00, 0x00 }; + int ret; + + /* init all GPIO LED's */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + /* enable all leds on PCA9552 */ + ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus); + if (ret) { + printf("ERROR: I2C get %d\n", ret); + return ret; + } + + ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev); + if (ret) { + printf("ERROR: PCA9552 probe failed\n"); + return ret; + } + + ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led)); + if (ret) { + printf("ERROR: PCA9552 write failed\n"); + return ret; + } + + mdelay(1); + return ret; +} +#endif /* !CONFIG_SPL_BUILD */ + +int checkboard(void) +{ + puts("Board: Capricorn\n"); + + /* + * Running build_info() doesn't work with current SCFW blob. + * Uncomment below call when new blob is available. + */ + /*build_info();*/ + + print_bootinfo(); + return 0; +} + +int board_init(void) +{ + setup_fec(); + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if (autodetect_str && (strcmp(autodetect_str, "yes") == 0)) + return 1; + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +#ifndef CONFIG_SPL_BUILD +int factoryset_read_eeprom(int i2c_addr); + +static int load_parameters_from_factoryset(void) +{ + int ret; + + ret = factoryset_read_eeprom(EEPROM_I2C_ADDR); + if (ret) + return ret; + + return factoryset_env_set(); +} + +int board_late_init(void) +{ + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + /* Init LEDs */ + if (board_led_init()) + printf("I2C LED init failed\n"); + + /* Set environment from factoryset */ + if (load_parameters_from_factoryset()) + printf("Loading factoryset parameters failed!\n"); + + return 0; +} + +/* Service button */ +#define MAX_PIN_NUMBER 128 +#define BOARD_DEFAULT_BUTTON_GPIO IMX_GPIO_NR(1, 31) + +unsigned char get_button_state(char * const envname, unsigned char def) +{ + int button = 0; + int gpio; + char *ptr_env; + + /* If button is not found we take default */ + ptr_env = env_get(envname); + if (!ptr_env) { + printf("Using default: %u\n", def); + gpio = def; + } else { + gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0); + if (gpio > MAX_PIN_NUMBER) + gpio = def; + } + + gpio_request(gpio, ""); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + + return button; +} + +/* + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int button = 0; + + button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO); + + if (argc > 1) + printf("Button state: %u\n", button); + + return button; +} + +U_BOOT_CMD( + usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton, + "Return the status of user button", + "[print]" +); + +#define ERST IMX_GPIO_NR(0, 3) + +static int +do_eth_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + gpio_request(ERST, "ERST"); + gpio_direction_output(ERST, 0); + udelay(200); + gpio_set_value(ERST, 1); + return 0; +} + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset, + "Reset eth phy", + "[print]" +); +#endif /* ! CONFIG_SPL_BUILD */ diff --git a/roms/u-boot/board/siemens/capricorn/imximage.cfg b/roms/u-boot/board/siemens/capricorn/imximage.cfg new file mode 100644 index 000000000..9f9df68e6 --- /dev/null +++ b/roms/u-boot/board/siemens/capricorn/imximage.cfg @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU capricorn-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/roms/u-boot/board/siemens/capricorn/spl.c b/roms/u-boot/board/siemens/capricorn/spl.c new file mode 100644 index 000000000..8e077d73a --- /dev/null +++ b/roms/u-boot/board/siemens/capricorn/spl.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Copyright 2019 Siemens AG + * + */ +#include <common.h> +#include <init.h> +#include <spl.h> +#include <dm.h> +#include <asm/global_data.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/roms/u-boot/board/siemens/capricorn/uboot-container.cfg b/roms/u-boot/board/siemens/capricorn/uboot-container.cfg new file mode 100644 index 000000000..816581181 --- /dev/null +++ b/roms/u-boot/board/siemens/capricorn/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QX +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/roms/u-boot/board/siemens/common/board.c b/roms/u-boot/board/siemens/common/board.c new file mode 100644 index 000000000..1bdf404ac --- /dev/null +++ b/roms/u-boot/board/siemens/common/board.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/board/ti/am335x/board.c + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <command.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <malloc.h> +#include <serial.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <watchdog.h> +#include <asm/mach-types.h> +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_set_bus_num(0); + + /* enable early the console */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + spl_siemens_board_init(); + board_init_ddr(); + + return; +} +#endif /* #ifdef CONFIG_SPL_BUILD */ + +#ifndef CONFIG_SPL_BUILD +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif /* defined(CONFIG_HW_WATCHDOG) */ + i2c_set_bus_num(0); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); +#ifdef CONFIG_MACH_TYPE + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; +#endif + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_FACTORYSET + factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); +#endif + + gpmc_init(); + +#ifdef CONFIG_NAND_CS_INIT + board_nand_cs_init(); +#endif +#ifdef CONFIG_VIDEO + board_video_init(); +#endif + + return 0; +} +#endif /* #ifndef CONFIG_SPL_BUILD */ + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +#ifndef CONFIG_SPL_BUILD + +#define MAX_NR_LEDS 10 +#define MAX_PIN_NUMBER 128 +#define STARTUP 0 + +#if defined(BOARD_DFU_BUTTON_GPIO) +unsigned char get_button_state(char * const envname, unsigned char def) +{ + int button = 0; + int gpio; + char *ptr_env; + + /* If button is not found we take default */ + ptr_env = env_get(envname); + if (NULL == ptr_env) { + gpio = def; + } else { + gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0); + if (gpio > MAX_PIN_NUMBER) + gpio = def; + } + + gpio_request(gpio, ""); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + + return button; +} +/** + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int button = 0; + button = get_button_state("button_dfu0", BOARD_DFU_BUTTON_GPIO); + button |= get_button_state("button_dfu1", BOARD_DFU_BUTTON_GPIO); + return button; +} + +U_BOOT_CMD( + dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the DFU button", + "" +); +#endif + +static int +do_usertestwdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + printf("\n\n\n Go into infinite loop\n\n\n"); + while (1) + ; + return 0; +}; + +U_BOOT_CMD( + testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt, + "Sends U-Boot into infinite loop", + "" +); + +/** + * Get led gpios from env and set them. + * The led define in environment need to need to be of the form ledN=NN,S0,S1 + * where N is an unsigned integer from 0 to 9 and S0 and S1 is 0 or 1. S0 + * defines the startup state of the led, S1 the special state of the led when + * it enters e.g. dfu mode. + */ +void set_env_gpios(unsigned char state) +{ + char *ptr_env; + char str_tmp[5]; /* must contain "ledX"*/ + unsigned char i, idx, pos1, pos2, ccount; + unsigned char gpio_n, gpio_s0, gpio_s1; + + for (i = 0; i < MAX_NR_LEDS; i++) { + sprintf(str_tmp, "led%d", i); + + /* If env var is not found we stop */ + ptr_env = env_get(str_tmp); + if (NULL == ptr_env) + break; + + /* Find sperators position */ + pos1 = 0; + pos2 = 0; + ccount = 0; + for (idx = 0; ptr_env[idx] != '\0'; idx++) { + if (ptr_env[idx] == ',') { + if (ccount++ < 1) + pos1 = idx; + else + pos2 = idx; + } + } + /* Bad led description skip this definition */ + if (pos2 <= pos1 || ccount > 2) + continue; + + /* Get pin number and request gpio */ + memset(str_tmp, 0, sizeof(str_tmp)); + strncpy(str_tmp, ptr_env, pos1*sizeof(char)); + gpio_n = (unsigned char)simple_strtoul(str_tmp, NULL, 0); + + /* Invalid gpio number skip definition */ + if (gpio_n > MAX_PIN_NUMBER) + continue; + + gpio_request(gpio_n, ""); + + if (state == STARTUP) { + /* get pin state 0 and set */ + memset(str_tmp, 0, sizeof(str_tmp)); + strncpy(str_tmp, ptr_env+pos1+1, + (pos2-pos1-1)*sizeof(char)); + gpio_s0 = (unsigned char)simple_strtoul(str_tmp, NULL, + 0); + + gpio_direction_output(gpio_n, gpio_s0); + + } else { + /* get pin state 1 and set */ + memset(str_tmp, 0, sizeof(str_tmp)); + strcpy(str_tmp, ptr_env+pos2+1); + gpio_s1 = (unsigned char)simple_strtoul(str_tmp, NULL, + 0); + gpio_direction_output(gpio_n, gpio_s1); + } + } /* loop through defined led in environment */ +} + +static int do_board_led(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if ((unsigned char)simple_strtoul(argv[1], NULL, 0) == STARTUP) + set_env_gpios(0); + else + set_env_gpios(1); + return 0; +}; + +U_BOOT_CMD( + draco_led, CONFIG_SYS_MAXARGS, 2, do_board_led, + "Set LEDs defined in environment", + "<0|1>" +); +#endif /* !CONFIG_SPL_BUILD */ diff --git a/roms/u-boot/board/siemens/common/factoryset.c b/roms/u-boot/board/siemens/common/factoryset.c new file mode 100644 index 000000000..2e3ae1a54 --- /dev/null +++ b/roms/u-boot/board/siemens/common/factoryset.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Read FactorySet information from EEPROM into global structure. + * (C) Copyright 2013 Siemens Schweiz AG + */ + +#if !defined(CONFIG_SPL_BUILD) + +#include <common.h> +#include <env.h> +#include <dm.h> +#include <env_internal.h> +#include <i2c.h> +#include <log.h> +#include <asm/io.h> +#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB) +#include <asm/arch/cpu.h> +#endif +#include <asm/arch/sys_proto.h> +#include <asm/unaligned.h> +#include <net.h> +#include <errno.h> +#include <g_dnl.h> +#include "factoryset.h" + +#define EEPR_PG_SZ 0x80 +#define EEPROM_FATORYSET_OFFSET 0x400 +#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ + +/* Global variable that contains necessary information from FactorySet */ +struct factorysetcontainer factory_dat; + +#define fact_get_char(i) *((char *)&eeprom_buf[i]) + +static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2) +{ + if (s1 == NULL) + return -1; + + while (*s1 == fact_get_char(i2++)) + if (*s1++ == '=') + return i2; + + if (*s1 == '\0' && fact_get_char(i2-1) == '=') + return i2; + + return -1; +} + +static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name, + uchar *buf, int len) +{ + int i, nxt = 0; + + for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) { + int val, n; + + for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= size) + return -1; + } + + val = fact_match(eeprom_buf, (uchar *)name, i); + if (val < 0) + continue; + + /* found; copy out */ + for (n = 0; n < len; ++n, ++buf) { + *buf = fact_get_char(val++); + if (*buf == '\0') + return n; + } + + if (n) + *--buf = '\0'; + + printf("env_buf [%d bytes] too small for value of \"%s\"\n", + len, name); + + return n; + } + return -1; +} + +static +int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, + uchar *name, uchar *buf, int len) +{ + int ret = -1; + int i, nxt = 0; + int c; + unsigned char end = 0xff; + unsigned char tmp; + + for (i = 0; fact_get_char(i) != end; i = nxt) { + nxt = i + 1; + if (fact_get_char(i) == '>') { + int pos; + int endpos; + int z; + int level = 0; + + c = strncmp((char *)&eeprom_buf[i + 1], (char *)record, + strlen((char *)record)); + if (c == 0) { + /* record found */ + pos = i + strlen((char *)record) + 2; + nxt = pos; + /* search for "<" */ + c = -1; + for (z = pos; fact_get_char(z) != end; z++) { + if (fact_get_char(z) == '<') { + if (level == 0) { + endpos = z; + nxt = endpos; + c = 0; + break; + } else { + level--; + } + } + if (fact_get_char(z) == '>') + level++; + } + } else { + continue; + } + if (c == 0) { + /* end found -> call get_factory_val */ + tmp = eeprom_buf[endpos]; + eeprom_buf[endpos] = end; + ret = get_factory_val(&eeprom_buf[pos], + endpos - pos, name, buf, len); + /* fix buffer */ + eeprom_buf[endpos] = tmp; + debug("%s: %s.%s = %s\n", + __func__, record, name, buf); + return ret; + } + } + } + return ret; +} + +int factoryset_read_eeprom(int i2c_addr) +{ + int i, pages = 0, size = 0; + unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH]; + unsigned char *cp, *cp1; +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *bus, *dev; + int ret; +#endif + +#if defined(CONFIG_DFU_OVER_USB) + factory_dat.usb_vendor_id = CONFIG_USB_GADGET_VENDOR_NUM; + factory_dat.usb_product_id = CONFIG_USB_GADGET_PRODUCT_NUM; +#endif + +#if CONFIG_IS_ENABLED(DM_I2C) + ret = uclass_get_device_by_seq(UCLASS_I2C, EEPROM_I2C_BUS, &bus); + if (ret) + goto err; + + ret = dm_i2c_probe(bus, i2c_addr, 0, &dev); + if (ret) + goto err; + + ret = i2c_set_chip_offset_len(dev, 2); + if (ret) + goto err; + + ret = dm_i2c_read(dev, EEPROM_FATORYSET_OFFSET, hdr, sizeof(hdr)); + if (ret) + goto err; +#else + if (i2c_probe(i2c_addr)) + goto err; + + if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr))) + goto err; +#endif + + if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) { + printf("FactorySet is not right in eeprom.\n"); + return 1; + } + + /* get FactorySet size */ + size = (hdr[2] << 8) + hdr[3] + sizeof(hdr); + if (size > 0x3bfa) + size = 0x3bfa; + + pages = size / EEPR_PG_SZ; + + /* + * read the eeprom using i2c + * I can not read entire eeprom in once, so separate into several + * times. Furthermore, fetch eeprom take longer time, so we fetch + * data after every time we got a record from eeprom + */ + debug("Read eeprom page :\n"); + for (i = 0; i < pages; i++) { +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_read(dev, (OFF_PG + i) * EEPR_PG_SZ, + eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ); + if (ret) + goto err; +#else + if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2, + eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ)) + goto err; +#endif + } + + if (size % EEPR_PG_SZ) { +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_read(dev, (OFF_PG + pages) * EEPR_PG_SZ, + eeprom_buf + (pages * EEPR_PG_SZ), + size % EEPR_PG_SZ); + if (ret) + goto err; +#else + if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2, + eeprom_buf + (pages * EEPR_PG_SZ), + (size % EEPR_PG_SZ))) + goto err; +#endif + } + + /* we do below just for eeprom align */ + for (i = 0; i < size; i++) + if (eeprom_buf[i] == '\n') + eeprom_buf[i] = 0; + + /* skip header */ + size -= sizeof(hdr); + cp = (uchar *)eeprom_buf + sizeof(hdr); + + /* get mac address */ + get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac", + buf, MAX_STRING_LENGTH); + cp1 = buf; + for (i = 0; i < 6; i++) { + factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16); + cp1 += 3; + } + +#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB) + /* get mac address for WLAN */ + ret = get_factory_record_val(cp, size, (uchar *)"WLAN1", (uchar *)"mac", + buf, MAX_STRING_LENGTH); + if (ret > 0) { + cp1 = buf; + for (i = 0; i < 6; i++) { + factory_dat.mac_wlan[i] = simple_strtoul((char *)cp1, + NULL, 16); + cp1 += 3; + } + } +#endif + +#if defined(CONFIG_DFU_OVER_USB) + /* read vid and pid for dfu mode */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"vid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_vendor_id = simple_strtoul((char *)buf, + NULL, 16); + } + + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"pid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_product_id = simple_strtoul((char *)buf, + NULL, 16); + } + printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id, + factory_dat.usb_product_id); +#endif +#if defined(CONFIG_VIDEO) + if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1", + (uchar *)"name", factory_dat.disp_name, + MAX_STRING_LENGTH)) { + debug("display name: %s\n", factory_dat.disp_name); + } +#endif + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"num", factory_dat.serial, + MAX_STRING_LENGTH)) { + debug("serial number: %s\n", factory_dat.serial); + } + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"ver", buf, + MAX_STRING_LENGTH)) { + factory_dat.version = simple_strtoul((char *)buf, + NULL, 16); + debug("version number: %d\n", factory_dat.version); + } + /* Get ASN from factory set if available */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"id", factory_dat.asn, + MAX_STRING_LENGTH)) { + debug("factoryset asn: %s\n", factory_dat.asn); + } else { + factory_dat.asn[0] = 0; + } + /* Get COMP/ver from factory set if available */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP", + (uchar *)"ver", + factory_dat.comp_version, + MAX_STRING_LENGTH)) { + debug("factoryset COMP/ver: %s\n", factory_dat.comp_version); + } else { + strcpy((char *)factory_dat.comp_version, "1.0"); + } + + return 0; + +err: + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; +} + +static int get_mac_from_efuse(uint8_t mac[6]) +{ +#ifdef CONFIG_AM33XX + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + uint32_t mac_hi, mac_lo; + + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + + mac[0] = mac_hi & 0xFF; + mac[1] = (mac_hi & 0xFF00) >> 8; + mac[2] = (mac_hi & 0xFF0000) >> 16; + mac[3] = (mac_hi & 0xFF000000) >> 24; + mac[4] = mac_lo & 0xFF; + mac[5] = (mac_lo & 0xFF00) >> 8; +#else + /* unhandled */ + memset(mac, 0, 6); +#endif + if (!is_valid_ethaddr(mac)) { + puts("Warning: ethaddr not set by FactorySet or E-fuse. "); + puts("Set <ethaddr> variable to overcome this.\n"); + return -1; + } + return 0; +} + +static int factoryset_mac_env_set(void) +{ + uint8_t mac_addr[6]; + + /* Set mac from factoryset or try reading E-fuse */ + debug("FactorySet: Set mac address\n"); + if (is_valid_ethaddr(factory_dat.mac)) { + memcpy(mac_addr, factory_dat.mac, 6); + } else { + debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n"); + if (get_mac_from_efuse(mac_addr) < 0) + return -1; + } + + eth_env_set_enetaddr("ethaddr", mac_addr); + +#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB) + eth_env_set_enetaddr("eth1addr", mac_addr); + + /* wlan mac */ + if (is_valid_ethaddr(factory_dat.mac_wlan)) + eth_env_set_enetaddr("eth2addr", factory_dat.mac_wlan); +#endif + return 0; +} + +static void factoryset_dtb_env_set(void) +{ + /* Set ASN in environment*/ + if (factory_dat.asn[0] != 0) { + env_set("dtb_name", (char *)factory_dat.asn); + } else { + /* dtb suffix gets added in load script */ + env_set("dtb_name", "default"); + } +} + +int factoryset_env_set(void) +{ + int ret = 0; + + factoryset_dtb_env_set(); + + if (factoryset_mac_env_set() < 0) + ret = -1; + + return ret; +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor); + put_unaligned(factory_dat.usb_product_id, &dev->idProduct); + g_dnl_set_serialnumber((char *)factory_dat.serial); + + return 0; +} + +int g_dnl_get_board_bcd_device_number(int gcnum) +{ + return factory_dat.version; +} +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/roms/u-boot/board/siemens/common/factoryset.h b/roms/u-boot/board/siemens/common/factoryset.h new file mode 100644 index 000000000..261a21768 --- /dev/null +++ b/roms/u-boot/board/siemens/common/factoryset.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + */ + +#ifndef __FACTORYSET_H +#define __FACTORYSET_H + +#define MAX_STRING_LENGTH 32 + +struct factorysetcontainer { + uchar mac[6]; +#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB) + uchar mac_wlan[6]; +#endif + int usb_vendor_id; + int usb_product_id; + int pxm50; +#if defined(CONFIG_VIDEO) + unsigned char disp_name[MAX_STRING_LENGTH]; +#endif + unsigned char serial[MAX_STRING_LENGTH]; + int version; + uchar asn[MAX_STRING_LENGTH]; + uchar comp_version[MAX_STRING_LENGTH]; +}; + +int factoryset_read_eeprom(int i2c_addr); +int factoryset_env_set(void); +extern struct factorysetcontainer factory_dat; + +#endif /* __FACTORYSET_H */ diff --git a/roms/u-boot/board/siemens/corvus/Kconfig b/roms/u-boot/board/siemens/corvus/Kconfig new file mode 100644 index 000000000..69fe0f072 --- /dev/null +++ b/roms/u-boot/board/siemens/corvus/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CORVUS + +config SYS_BOARD + default "corvus" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "corvus" + +endif diff --git a/roms/u-boot/board/siemens/corvus/MAINTAINERS b/roms/u-boot/board/siemens/corvus/MAINTAINERS new file mode 100644 index 000000000..59176aae5 --- /dev/null +++ b/roms/u-boot/board/siemens/corvus/MAINTAINERS @@ -0,0 +1,6 @@ +CORVUS BOARD +M: Heiko Schocher <hs@denx.de> +S: Maintained +F: board/siemens/corvus/ +F: include/configs/corvus.h +F: configs/corvus_defconfig diff --git a/roms/u-boot/board/siemens/corvus/Makefile b/roms/u-boot/board/siemens/corvus/Makefile new file mode 100644 index 000000000..c67acc613 --- /dev/null +++ b/roms/u-boot/board/siemens/corvus/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile for siemens CORVUS (AT91SAM9G45) based board +# (C) Copyright 2013 Siemens AG +# +# Based on: +# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> + +obj-y += board.o diff --git a/roms/u-boot/board/siemens/corvus/board.c b/roms/u-boot/board/siemens/corvus/board.c new file mode 100644 index 000000000..a6e1737be --- /dev/null +++ b/roms/u-boot/board/siemens/corvus/board.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for Siemens CORVUS (AT91SAM9G45) based board + * (C) Copyright 2013 Siemens AG + * + * Based on: + * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <log.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_serial.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/arch/clk.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#ifndef CONFIG_DM_ETH +#include <netdev.h> +#endif +#include <spi.h> + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +#include <asm/arch/atmel_usba_udc.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void corvus_request_gpio(void) +{ + gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(AT91_PIN_PD7, "d0"); + gpio_request(AT91_PIN_PD8, "d1"); + gpio_request(AT91_PIN_PA12, "d2"); + gpio_request(AT91_PIN_PA13, "d3"); + gpio_request(AT91_PIN_PA15, "d4"); + gpio_request(AT91_PIN_PB7, "recovery button"); + gpio_request(AT91_PIN_PD1, "USB0"); + gpio_request(AT91_PIN_PD3, "USB1"); + gpio_request(AT91_PIN_PB18, "SPICS1"); + gpio_request(AT91_PIN_PB3, "SPICS0"); + gpio_request(CONFIG_RED_LED, "red led"); + gpio_request(CONFIG_GREEN_LED, "green led"); +} + +static void corvus_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOA); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); +} + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void spl_board_init(void) +{ + corvus_request_gpio(); + /* + * For on the sam9m10g45ek board, the chip wm9711 stay in the test + * mode, so it need do some action to exit mode. + */ + at91_set_gpio_output(AT91_PIN_PD7, 0); + at91_set_gpio_output(AT91_PIN_PD8, 0); + at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); + at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + + corvus_nand_hw_init(); + + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PB7, 1); + + /* check if button is pressed */ + if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { + u32 boot_device; + + debug("Recovery button pressed\n"); + boot_device = spl_boot_device(); + switch (boot_device) { +#ifdef CONFIG_SPL_NAND_SUPPORT + case BOOT_DEVICE_NAND: + nand_init(); + spl_nand_erase_one(0, 0); + break; +#endif + } + } +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DQMS_SHARED | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3); + ddr2->rtr = 0x24b; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ + 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ + 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct atmel_mpddrc_config ddr2; + + ddr2_conf(&ddr2); + + at91_system_clk_enable(AT91_PMC_DDR); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); +} +#endif + +#ifdef CONFIG_CMD_USB +static void taurus_usb_hw_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIODE); + + at91_set_gpio_output(AT91_PIN_PD1, 0); + at91_set_gpio_output(AT91_PIN_PD3, 0); +} +#endif + +#ifdef CONFIG_MACB +static void corvus_macb_hw_init(void) +{ + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); + + at91_phy_reset(); + + /* Re-enable pull-up */ + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); + + /* And the pins. */ + at91_macb_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + corvus_request_gpio(); + return 0; +} + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +/* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */ +void at91_udp_hw_init(void) +{ + /* Enable UPLL clock */ + at91_upll_clk_enable(); + + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* we have to request the gpios again after relocation */ + corvus_request_gpio(); +#ifdef CONFIG_CMD_NAND + corvus_nand_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 4); +#endif +#ifdef CONFIG_MACB + corvus_macb_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + taurus_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); + usba_udc_probe(&pdata); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifndef CONFIG_DM_ETH +int board_eth_init(struct bd_info *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); +#endif + return rc; +} +#endif + +/* SPI chip select control */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < 2; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 0); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 0); + break; + } +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 1); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 1); + break; + } +} + +static struct atmel_serial_plat at91sam9260_serial_plat = { + .base_addr = ATMEL_BASE_DBGU, +}; + +U_BOOT_DRVINFO(at91sam9260_serial) = { + .name = "serial_atmel", + .plat = &at91sam9260_serial_plat, +}; diff --git a/roms/u-boot/board/siemens/draco/Kconfig b/roms/u-boot/board/siemens/draco/Kconfig new file mode 100644 index 000000000..a699c7d46 --- /dev/null +++ b/roms/u-boot/board/siemens/draco/Kconfig @@ -0,0 +1,63 @@ +if TARGET_DRACO + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "draco" + +endif + +if TARGET_THUBAN + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "thuban" + +endif + +if TARGET_RASTABAN + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "rastaban" + +endif + +if TARGET_ETAMIN + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "etamin" + +endif diff --git a/roms/u-boot/board/siemens/draco/MAINTAINERS b/roms/u-boot/board/siemens/draco/MAINTAINERS new file mode 100644 index 000000000..c73f18c00 --- /dev/null +++ b/roms/u-boot/board/siemens/draco/MAINTAINERS @@ -0,0 +1,11 @@ +DRACO BOARD +M: Samuel Egli <samuel.egli@siemens.com> +S: Maintained +F: board/siemens/draco/ +F: include/configs/draco.h +F: configs/draco_defconfig +F: configs/etamin_defconfig +F: include/configs/thuban.h +F: configs/thuban_defconfig +F: include/configs/rastaban.h +F: configs/rastaban_defconfig diff --git a/roms/u-boot/board/siemens/draco/Makefile b/roms/u-boot/board/siemens/draco/Makefile new file mode 100644 index 000000000..3e3394a86 --- /dev/null +++ b/roms/u-boot/board/siemens/draco/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + +ifdef CONFIG_SPL_BUILD +obj-y := mux.o +endif + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/factoryset.o +endif diff --git a/roms/u-boot/board/siemens/draco/board.c b/roms/u-boot/board/siemens/draco/board.c new file mode 100644 index 000000000..01fdfb5cb --- /dev/null +++ b/roms/u-boot/board/siemens/draco/board.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for TI AM335X based draco board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * + * Board functions for TI AM335X based boards + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <command.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <net.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <watchdog.h> +#include <linux/delay.h> +#include "board.h" +#include "../common/factoryset.h" +#include <nand.h> + +#ifdef CONFIG_SPL_BUILD +static struct draco_baseboard_id __section(".data") settings; + +#if DDR_PLL_FREQ == 303 +#if !defined(CONFIG_TARGET_ETAMIN) +/* Default@303MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, + 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32, + 0x0000093B, 0x0000014A, + "default name @303MHz \0", + "default marking \0", +}; +#else +/* etamin board */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F, + 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2, + 0x0000093B, 0x0000018A, + "test-etamin \0", + "generic-8Gbit \0", +}; +#endif +#elif DDR_PLL_FREQ == 400 +/* Default@400MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab, + 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232, + 0x00000618, 0x0000014A, + "default name @400MHz \0", + "default marking \0", +}; +#endif + +static void set_default_ddr3_timings(void) +{ + printf("Set default DDR3 settings\n"); + settings.ddr3 = ddr3_default; +} + +static void print_ddr3_timings(void) +{ + printf("\nDDR3\n"); + printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); + printf("device:\t\t%s\n", settings.ddr3.manu_name); + printf("marking:\t%s\n", settings.ddr3.manu_marking); + printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom", + "default", "diff"); + PRINTARGS(magic); + PRINTARGS(version); + PRINTARGS(ddr3_sratio); + PRINTARGS(iclkout); + + PRINTARGS(dt0rdsratio0); + PRINTARGS(dt0wdsratio0); + PRINTARGS(dt0fwsratio0); + PRINTARGS(dt0wrsratio0); + + PRINTARGS(sdram_tim1); + PRINTARGS(sdram_tim2); + PRINTARGS(sdram_tim3); + + PRINTARGS(emif_ddr_phy_ctlr_1); + + PRINTARGS(sdram_config); + PRINTARGS(ref_ctrl); + PRINTARGS(ioctr_val); +} + +static void print_chip_data(void) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + printf("\nCPU BOARD\n"); + printf("device: \t'%s'\n", settings.chip.sdevname); + printf("hw version: \t'%s'\n", settings.chip.shwver); + printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m); +} +#endif /* CONFIG_SPL_BUILD */ + +#define AM335X_NAND_ECC_MASK 0x0f +#define AM335X_NAND_ECC_TYPE_16 0x02 + +static int ecc_type; + +struct am335x_nand_geometry { + u32 magic; + u8 nand_geo_addr; + u8 nand_geo_page; + u8 nand_bus; +}; + +static int draco_read_nand_geometry(void) +{ + struct am335x_nand_geometry geo; + + /* Read NAND geometry */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2, + (uchar *)&geo, sizeof(struct am335x_nand_geometry))) { + printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + if (geo.magic != 0xa657b310) { + printf("%s: bad magic: %x\n", __func__, geo.magic); + return -EFAULT; + } + if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16) + ecc_type = 16; + else + ecc_type = 8; + + return 0; +} + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; + } + +#ifdef CONFIG_SPL_BUILD + /* Read Siemens eeprom data (DDR3) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); + set_default_ddr3_timings(); + } + /* Read Siemens eeprom data (CHIP) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + (uchar *)&settings.chip, sizeof(settings.chip))) + printf("Could not read chip settings\n"); + + if (ddr3_default.magic == settings.ddr3.magic && + ddr3_default.version == settings.ddr3.version) { + printf("Using DDR3 settings from EEPROM\n"); + } else { + if (ddr3_default.magic != settings.ddr3.magic) + printf("Warning: No valid DDR3 data in eeprom.\n"); + if (ddr3_default.version != settings.ddr3.version) + printf("Warning: DDR3 data version does not match.\n"); + + printf("Using default settings\n"); + set_default_ddr3_timings(); + } + + if (MAGIC_CHIP == settings.chip.magic) + print_chip_data(); + else + printf("Warning: No chip data in eeprom\n"); + + print_ddr3_timings(); + + return draco_read_nand_geometry(); +#endif + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs draco_ddr3_emif_reg_data = { + .zq_config = 0x50074BE4, +}; + +struct ddr_data draco_ddr3_data = { +}; + +struct cmd_control draco_ddr3_cmd_ctrl_data = { +}; + +struct ctrl_ioregs draco_ddr3_ioregs = { +}; + + /* pass values from eeprom */ + draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; + draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; + draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; + draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = + settings.ddr3.emif_ddr_phy_ctlr_1; + draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000; + draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; + + draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; + draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; + draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; + draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; + + draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; + + draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, + &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + + ret = draco_read_nand_geometry(); + if (ret != 0) + return ret; + + nand_curr_device = 0; + omap_nand_switch_ecc(1, ecc_type); +#ifdef CONFIG_TARGET_ETAMIN + nand_curr_device = 1; + omap_nand_switch_ecc(1, ecc_type); +#endif +#ifdef CONFIG_FACTORYSET + /* Set ASN in environment*/ + if (factory_dat.asn[0] != 0) { + env_set("dtb_name", (char *)factory_dat.asn); + } else { + /* dtb suffix gets added in load script */ + env_set("dtb_name", "am335x-draco"); + } +#else + env_set("dtb_name", "am335x-draco"); +#endif + + return 0; +} +#endif + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) +int board_eth_init(struct bd_info *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + + factoryset_env_set(); + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} + +static int do_switch_reset(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + /* Reset SMSC LAN9303 switch for default configuration */ + gpio_request(GPIO_LAN9303_NRST, "nRST"); + gpio_direction_output(GPIO_LAN9303_NRST, 0); + /* assert active low reset for 200us */ + udelay(200); + gpio_set_value(GPIO_LAN9303_NRST, 1); + + return 0; +}; + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, + "Reset LAN9303 switch via its reset pin", + "" +); +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#ifdef CONFIG_NAND_CS_INIT +/* GPMC definitions for second nand cs1 */ +static const u32 gpmc_nand_config[] = { + ETAMIN_NAND_GPMC_CONFIG1, + ETAMIN_NAND_GPMC_CONFIG2, + ETAMIN_NAND_GPMC_CONFIG3, + ETAMIN_NAND_GPMC_CONFIG4, + ETAMIN_NAND_GPMC_CONFIG5, + ETAMIN_NAND_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + +static void board_nand_cs_init(void) +{ + enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1], + 0x18000000, GPMC_SIZE_16M); +} +#endif + +#include "../common/board.c" diff --git a/roms/u-boot/board/siemens/draco/board.h b/roms/u-boot/board/siemens/draco/board.h new file mode 100644 index 000000000..7c29a45c0 --- /dev/null +++ b/roms/u-boot/board/siemens/draco/board.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define PARGS(x) #x , /* Parameter Name */ \ + settings.ddr3.x, /* EEPROM Value */ \ + ddr3_default.x, /* Default Value */ \ + settings.ddr3.x-ddr3_default.x /* Difference */ + +#define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y)) + +#define MAGIC_CHIP 0x50494843 + +/* Automatic generated definition */ +/* Wed, 16 Apr 2014 16:50:41 +0200 */ +/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ +struct ddr3_data { + unsigned int magic; /* 0x33524444 */ + unsigned int version; /* 0x56312e35 */ + unsigned short int ddr3_sratio; /* 0x0080 */ + unsigned short int iclkout; /* 0x0000 */ + unsigned short int dt0rdsratio0; /* 0x003A */ + unsigned short int dt0wdsratio0; /* 0x003F */ + unsigned short int dt0fwsratio0; /* 0x009F */ + unsigned short int dt0wrsratio0; /* 0x0079 */ + unsigned int sdram_tim1; /* 0x0888A39B */ + unsigned int sdram_tim2; /* 0x26247FDA */ + unsigned int sdram_tim3; /* 0x501F821F */ + unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ + unsigned int sdram_config; /* 0x61A44A32 */ + unsigned int ref_ctrl; /* 0x0000093B */ + unsigned int ioctr_val; /* 0x0000014A */ + char manu_name[32]; /* "default@303MHz \0" */ + char manu_marking[32]; /* "default \0" */ +}; + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; +}; + +struct draco_baseboard_id { + struct ddr3_data ddr3; + struct chip_data chip; +}; + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); + +/* Forwared declaration, defined in common board.c */ +void set_env_gpios(unsigned char state); +#endif diff --git a/roms/u-boot/board/siemens/draco/mux.c b/roms/u-boot/board/siemens/draco/mux.c new file mode 100644 index 000000000..3f2d41bef --- /dev/null +++ b/roms/u-boot/board/siemens/draco/mux.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * pinmux setup for siemens draco board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN}, /* NAND_CS1 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux gpios_pin_mux[] = { + /* DFU button GPIO0_27*/ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ + {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ + /* Triacs in HW Rev 2 */ + {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/ + {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/ + {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/ + /* Triacs initial HW Rev */ + {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */ + {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */ + {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */ + {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */ + {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */ + {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */ + {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */ + /* Remaining pins that were not used in this file */ + {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, + /* nRST for SMSC LAN9303 switch - GPIO2_24 */ + {OFFSET(lcd_pclk), MODE(7) | PULLUDEN | PULLUP_EN }, /* LAN9303 nRST */ + {-1}, +}; + +static struct module_pin_mux ethernet_pin_mux[] = { + {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + enable_uart3_pin_mux(); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ethernet_pin_mux); + configure_module_pin_mux(gpios_pin_mux); +} diff --git a/roms/u-boot/board/siemens/pxm2/Kconfig b/roms/u-boot/board/siemens/pxm2/Kconfig new file mode 100644 index 000000000..62604ecb3 --- /dev/null +++ b/roms/u-boot/board/siemens/pxm2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PXM2 + +config SYS_BOARD + default "pxm2" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "pxm2" + +endif diff --git a/roms/u-boot/board/siemens/pxm2/MAINTAINERS b/roms/u-boot/board/siemens/pxm2/MAINTAINERS new file mode 100644 index 000000000..dc02fe87c --- /dev/null +++ b/roms/u-boot/board/siemens/pxm2/MAINTAINERS @@ -0,0 +1,6 @@ +PXM2 BOARD +M: Samuel Egli <samuel.egli@siemens.com> +S: Maintained +F: board/siemens/pxm2/ +F: include/configs/pxm2.h +F: configs/pxm2_defconfig diff --git a/roms/u-boot/board/siemens/pxm2/Makefile b/roms/u-boot/board/siemens/pxm2/Makefile new file mode 100644 index 000000000..3e3394a86 --- /dev/null +++ b/roms/u-boot/board/siemens/pxm2/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + +ifdef CONFIG_SPL_BUILD +obj-y := mux.o +endif + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/factoryset.o +endif diff --git a/roms/u-boot/board/siemens/pxm2/board.c b/roms/u-boot/board/siemens/pxm2/board.c new file mode 100644 index 000000000..b5e9b4242 --- /dev/null +++ b/roms/u-boot/board/siemens/pxm2/board.c @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for TI AM335X based pxm2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <log.h> +#include <malloc.h> +#include <net.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include "../../../drivers/video/da8xx-fb.h" +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <watchdog.h> +#include "board.h" +#include "../common/factoryset.h" +#include "pmic.h" +#include <nand.h> +#include <bmp_layout.h> + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs pxm2_ddr3_emif_reg_data = { + .sdram_config = 0x41805332, + .sdram_tim1 = 0x666b3c9, + .sdram_tim2 = 0x243631ca, + .sdram_tim3 = 0x33f, + .emif_ddr_phy_ctlr_1 = 0x100005, + .zq_config = 0, + .ref_ctrl = 0x81a, +}; + +struct ddr_data pxm2_ddr3_data = { + .datardsratio0 = 0x81204812, + .datawdsratio0 = 0, + .datafwsratio0 = 0x8020080, + .datawrsratio0 = 0x4010040, +}; + +struct cmd_control pxm2_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x80, + .cmd0iclkout = 0, + .cmd1csratio = 0x80, + .cmd1iclkout = 0, + .cmd2csratio = 0x80, + .cmd2iclkout = 0, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = DDR_IOCTRL_VAL, + .cm1ioctl = DDR_IOCTRL_VAL, + .cm2ioctl = DDR_IOCTRL_VAL, + .dt0ioctl = DDR_IOCTRL_VAL, + .dt1ioctl = DDR_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, + &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); +} + +/* + * voltage switching for MPU frequency switching. + * @module = mpu - 0, core - 1 + * @vddx_op_vol_sel = vdd voltage to set + */ + +#define MPU 0 +#define CORE 1 + +int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf[4]; + unsigned int reg_offset; + + if (module == MPU) + reg_offset = PMIC_VDD1_OP_REG; + else + reg_offset = PMIC_VDD2_OP_REG; + + /* Select VDDx OP */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_CMD_MASK; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + /* Configure VDDx OP Voltage */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_SEL_MASK; + buf[0] |= vddx_op_vol_sel; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} + +#define OSC (V_OSCK/1000000) + +const struct dpll_params dpll_mpu_pxm2 = { + 720, OSC-1, 1, -1, -1, -1, -1}; + +void spl_siemens_board_init(void) +{ + uchar buf[4]; + /* + * pxm2 PMIC code. All boards currently want an MPU voltage + * of 1.2625V and CORE voltage of 1.1375V to operate at + * 720MHz. + */ + if (i2c_probe(PMIC_CTRL_I2C_ADDR)) + return; + + /* VDD1/2 voltage selection register access by control i/f */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + /* Frequency switching for OPP 120 */ + if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || + voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { + printf("voltage update failed\n"); + } +} +#endif /* if def CONFIG_SPL_BUILD */ + +int read_eeprom(void) +{ + /* nothing ToDo here for this board */ + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) +int board_eth_init(struct bd_info *bis) +{ + int n = 0; +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#ifdef CONFIG_FACTORYSET + int rv; + if (!is_valid_ethaddr(factory_dat.mac)) + printf("Error: no valid mac address\n"); + else + eth_env_set_enetaddr("ethaddr", factory_dat.mac); +#endif /* #ifdef CONFIG_FACTORYSET */ + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* AUO G156XW01 V1 */ + [0] = { + .name = "AUO_G156XW01_V1", + .width = 1376, + .height = 768, + .hfp = 14, + .hbp = 64, + .hsw = 56, + .vfp = 1, + .vbp = 28, + .vsw = 3, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* AUO B101EVN06 V0 */ + [1] = { + .name = "AUO_B101EVN06_V0", + .width = 1280, + .height = 800, + .hfp = 52, + .hbp = 84, + .hsw = 36, + .vfp = 3, + .vbp = 14, + .vsw = 6, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* + * Settings from factoryset + * stored in EEPROM + */ + [2] = { + .name = "factoryset", + .width = 0, + .height = 0, + .hfp = 0, + .hbp = 0, + .hsw = 0, + .vfp = 0, + .vbp = 0, + .vsw = 0, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, +}; + +static const struct display_panel disp_panel = { + WVGA, + 32, + 16, + COLOR_ACTIVE, +}; + +static const struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 32, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_backlight(void) +{ + set_gpio(BOARD_LCD_POWER, 1); + set_gpio(BOARD_BACK_LIGHT, 1); + set_gpio(BOARD_TOUCH_POWER, 1); + return 0; +} + +static int enable_pwm(void) +{ + struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE; + struct pwmss_ecap_regs *ecap; + int ticks = PWM_TICKS; + int duty = PWM_DUTY; + + ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE; + /* enable clock */ + setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN); + /* TimeStam Counter register */ + writel(0xdb9, &ecap->tsctr); + /* config period */ + writel(ticks - 1, &ecap->cap3); + writel(ticks - 1, &ecap->cap1); + setbits_le16(&ecap->ecctl2, + (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0)); + /* config duty */ + writel(duty, &ecap->cap2); + writel(duty, &ecap->cap4); + /* start */ + setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN); + return 0; +} + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->epwmss0clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + + return 0; +} + +static int board_video_init(void) +{ + conf_disp_pll(24, 1); + if (factory_dat.pxm50) + da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); + else + da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); + + enable_pwm(); + enable_backlight(); + + return 0; +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + + omap_nand_switch_ecc(1, 8); + +#ifdef CONFIG_FACTORYSET + if (factory_dat.asn[0] != 0) { + char tmp[2 * MAX_STRING_LENGTH + 2]; + + if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0) + factory_dat.pxm50 = 1; + else + factory_dat.pxm50 = 0; + sprintf(tmp, "%s_%s", factory_dat.asn, + factory_dat.comp_version); + ret = env_set("boardid", tmp); + if (ret) + printf("error setting board id\n"); + } else { + factory_dat.pxm50 = 1; + ret = env_set("boardid", "PXM50_1.0"); + if (ret) + printf("error setting board id\n"); + } + debug("PXM50: %d\n", factory_dat.pxm50); +#endif + + return 0; +} +#endif + +#include "../common/board.c" diff --git a/roms/u-boot/board/siemens/pxm2/board.h b/roms/u-boot/board/siemens/pxm2/board.h new file mode 100644 index 000000000..af21fc474 --- /dev/null +++ b/roms/u-boot/board/siemens/pxm2/board.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/roms/u-boot/board/siemens/pxm2/mux.c b/roms/u-boot/board/siemens/pxm2/mux.c new file mode 100644 index 000000000..2f35bb4a7 --- /dev/null +++ b/roms/u-boot/board/siemens/pxm2/mux.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * pinmux setup for siemens pxm2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */ + {-1}, +}; + +#ifdef CONFIG_MTD_RAW_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */ + {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */ + {-1}, +}; +#endif + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +#ifndef CONFIG_NO_ETH +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */ + {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */ + {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; +#endif + +#ifdef CONFIG_MMC +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */ + {-1}, +}; +#endif + +static struct module_pin_mux lcdc_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */ + {-1}, +}; + +static struct module_pin_mux ecap0_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/ + {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */ + {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */ + {-1}, +}; +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); +#ifdef CONFIG_MTD_RAW_NAND + configure_module_pin_mux(nand_pin_mux); +#endif +#ifndef CONFIG_NO_ETH + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); +#endif +#ifdef CONFIG_MMC + configure_module_pin_mux(mmc0_pin_mux); +#endif + configure_module_pin_mux(lcdc_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(ecap0_pin_mux); +} diff --git a/roms/u-boot/board/siemens/pxm2/pmic.h b/roms/u-boot/board/siemens/pxm2/pmic.h new file mode 100644 index 000000000..37660460a --- /dev/null +++ b/roms/u-boot/board/siemens/pxm2/pmic.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef PMIC_H +#define PMIC_H + +/* + * The PMIC on this board is a TPS65910. + */ + +#define PMIC_SR_I2C_ADDR 0x12 +#define PMIC_CTRL_I2C_ADDR 0x2D +/* PMIC Register offsets */ +#define PMIC_VDD1_REG 0x21 +#define PMIC_VDD1_OP_REG 0x22 +#define PMIC_VDD2_REG 0x24 +#define PMIC_VDD2_OP_REG 0x25 +#define PMIC_DEVCTRL_REG 0x3f + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define PMIC_VGAIN_SEL_MASK (0x3 << 6) +#define PMIC_ILMAX_MASK (0x1 << 5) +#define PMIC_TSTEP_MASK (0x7 << 2) +#define PMIC_ST_MASK (0x3) + +#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) +#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) +#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define PMIC_REG_ILMAX_1_0_A (0x0 << 5) +#define PMIC_REG_ILMAX_1_5_A (0x1 << 5) + +#define PMIC_REG_TSTEP_ (0x0 << 2) +#define PMIC_REG_TSTEP_12_5 (0x1 << 2) +#define PMIC_REG_TSTEP_9_4 (0x2 << 2) +#define PMIC_REG_TSTEP_7_5 (0x3 << 2) +#define PMIC_REG_TSTEP_6_25 (0x4 << 2) +#define PMIC_REG_TSTEP_4_7 (0x5 << 2) +#define PMIC_REG_TSTEP_3_12 (0x6 << 2) +#define PMIC_REG_TSTEP_2_5 (0x7 << 2) + +#define PMIC_REG_ST_OFF (0x0) +#define PMIC_REG_ST_ON_HI_POW (0x1) +#define PMIC_REG_ST_OFF_1 (0x2) +#define PMIC_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define PMIC_OP_REG_SEL (0x7F) + +#define PMIC_OP_REG_CMD_MASK (0x1 << 7) +#define PMIC_OP_REG_CMD_OP (0x0 << 7) +#define PMIC_OP_REG_CMD_SR (0x1 << 7) + +#define PMIC_OP_REG_SEL_MASK (0x7F) +#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +#endif diff --git a/roms/u-boot/board/siemens/rut/Kconfig b/roms/u-boot/board/siemens/rut/Kconfig new file mode 100644 index 000000000..337107766 --- /dev/null +++ b/roms/u-boot/board/siemens/rut/Kconfig @@ -0,0 +1,15 @@ +if TARGET_RUT + +config SYS_BOARD + default "rut" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "rut" + +endif diff --git a/roms/u-boot/board/siemens/rut/MAINTAINERS b/roms/u-boot/board/siemens/rut/MAINTAINERS new file mode 100644 index 000000000..1e9271090 --- /dev/null +++ b/roms/u-boot/board/siemens/rut/MAINTAINERS @@ -0,0 +1,6 @@ +RUT BOARD +M: Samuel Egli <samuel.egli@siemens.com> +S: Maintained +F: board/siemens/rut/ +F: include/configs/rut.h +F: configs/rut_defconfig diff --git a/roms/u-boot/board/siemens/rut/Makefile b/roms/u-boot/board/siemens/rut/Makefile new file mode 100644 index 000000000..3e3394a86 --- /dev/null +++ b/roms/u-boot/board/siemens/rut/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + +ifdef CONFIG_SPL_BUILD +obj-y := mux.o +endif + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/factoryset.o +endif diff --git a/roms/u-boot/board/siemens/rut/board.c b/roms/u-boot/board/siemens/rut/board.c new file mode 100644 index 000000000..e0f232d3b --- /dev/null +++ b/roms/u-boot/board/siemens/rut/board.c @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for TI AM335X based rut board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <malloc.h> +#include <net.h> +#include <spi.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <video.h> +#include <watchdog.h> +#include <linux/delay.h> +#include "board.h" +#include "../common/factoryset.h" +#include "../../../drivers/video/da8xx-fb.h" + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs rut_ddr3_emif_reg_data = { + .sdram_config = 0x61C04AB2, + .sdram_tim1 = 0x0888A39B, + .sdram_tim2 = 0x26337FDA, + .sdram_tim3 = 0x501F830F, + .emif_ddr_phy_ctlr_1 = 0x6, + .zq_config = 0x50074BE4, + .ref_ctrl = 0x93B, +}; + +struct ddr_data rut_ddr3_data = { + .datardsratio0 = 0x3b, + .datawdsratio0 = 0x85, + .datafwsratio0 = 0x100, + .datawrsratio0 = 0xc1, +}; + +struct cmd_control rut_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x40, + .cmd0iclkout = 1, + .cmd1csratio = 0x40, + .cmd1iclkout = 1, + .cmd2csratio = 0x40, + .cmd2iclkout = 1, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = RUT_IOCTRL_VAL, + .cm1ioctl = RUT_IOCTRL_VAL, + .cm2ioctl = RUT_IOCTRL_VAL, + .dt0ioctl = RUT_IOCTRL_VAL, + .dt1ioctl = RUT_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data, + &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); +} + +static int request_and_pulse_reset(int gpio, const char *name) +{ + int ret; + const int delay_us = 2000; /* 2ms */ + + ret = gpio_request(gpio, name); + if (ret < 0) { + printf("%s: Unable to request %s\n", __func__, name); + goto err; + } + + ret = gpio_direction_output(gpio, 0); + if (ret < 0) { + printf("%s: Unable to set %s as output\n", __func__, name); + goto err_free_gpio; + } + + udelay(delay_us); + + gpio_set_value(gpio, 1); + + return 0; + +err_free_gpio: + gpio_free(gpio); +err: + return ret; +} + +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) +#define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18) +#define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18) +#define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19) + +#define REQUEST_AND_PULSE_RESET(N) \ + request_and_pulse_reset(N, #N); + +static void spl_siemens_board_init(void) +{ + REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO); + REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO); + REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO); +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if defined(CONFIG_DRIVER_TI_CPSW) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) +int board_eth_init(struct bd_info *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + +#ifndef CONFIG_SPL_BUILD + factoryset_env_set(); +#endif + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_HW_WATCHDOG) +static bool hw_watchdog_init_done; +static int hw_watchdog_trigger_level; + +void hw_watchdog_reset(void) +{ + if (!hw_watchdog_init_done) + return; + + hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1; + gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); +} + +void hw_watchdog_init(void) +{ + gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); + gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); + + hw_watchdog_reset(); + + hw_watchdog_init_done = 1; +} +#endif /* defined(CONFIG_HW_WATCHDOG) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */ + [0] = { + .name = "KWH043MC17-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */ + [1] = { + .name = "KWH043ST20-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */ + [2] = { + .name = "MI0430VT-1", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, +}; + +static const struct display_panel disp_panels[] = { + [0] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [1] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [2] = { + WVGA, + 24, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, +}; + +static const struct lcd_ctrl_config lcd_cfgs[] = { + [0] = { + &disp_panels[0], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [1] = { + &disp_panels[1], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [2] = { + &disp_panels[2], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 24, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; +#endif + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->spi1clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ + writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ + writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK, + &cmwkup->clkmoddplldisp); /* 0x98 */ +#endif + return 0; +} + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_lcd(void) +{ + unsigned char buf[1]; + + set_gpio(BOARD_LCD_RESET, 0); + mdelay(1); + set_gpio(BOARD_LCD_RESET, 1); + mdelay(1); + + /* spi lcd init */ + kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0); + + /* backlight on */ + buf[0] = 0xf; + i2c_write(0x24, 0x7, 1, buf, 1); + buf[0] = 0x3f; + i2c_write(0x24, 0x8, 1, buf, 1); + return 0; +} + +int arch_early_init_r(void) +{ + enable_lcd(); + return 0; +} + +static int board_video_init(void) +{ + int i; + int anzdisp = ARRAY_SIZE(lcd_panels); + int display = 1; + + for (i = 0; i < anzdisp; i++) { + if (strncmp((const char *)factory_dat.disp_name, + lcd_panels[i].name, + strlen((const char *)factory_dat.disp_name)) == 0) { + printf("DISPLAY: %s\n", factory_dat.disp_name); + break; + } + } + if (i == anzdisp) { + i = 1; + printf("%s: %s not found, using default %s\n", __func__, + factory_dat.disp_name, lcd_panels[i].name); + } + conf_disp_pll(24, 1); + da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display], + lcd_cfgs[display].bpp); + + return 0; +} +#endif /* ifdef CONFIG_VIDEO */ + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + char tmp[2 * MAX_STRING_LENGTH + 2]; + + omap_nand_switch_ecc(1, 8); + + if (factory_dat.asn[0] != 0) + sprintf(tmp, "%s_%s", factory_dat.asn, + factory_dat.comp_version); + else + strcpy(tmp, "QMX7.E38_4.0"); + + ret = env_set("boardid", tmp); + if (ret) + printf("error setting board id\n"); + + return 0; +} +#endif + +#include "../common/board.c" diff --git a/roms/u-boot/board/siemens/rut/board.h b/roms/u-boot/board/siemens/rut/board.h new file mode 100644 index 000000000..af21fc474 --- /dev/null +++ b/roms/u-boot/board/siemens/rut/board.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/roms/u-boot/board/siemens/rut/mux.c b/roms/u-boot/board/siemens/rut/mux.c new file mode 100644 index 000000000..d80120bbd --- /dev/null +++ b/roms/u-boot/board/siemens/rut/mux.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * pinmux setup for siemens rut board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux ddr_pin_mux[] = { + {OFFSET(ddr_resetn), (MODE(0))}, + {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ck), (MODE(0))}, + {OFFSET(ddr_nck), (MODE(0))}, + {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_odt), (MODE(0))}, + {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(gpmc_ad8), (MODE(1))}, + {OFFSET(gpmc_ad9), (MODE(1))}, + {OFFSET(gpmc_ad10), (MODE(1))}, + {OFFSET(gpmc_ad11), (MODE(1))}, + {OFFSET(gpmc_ad12), (MODE(1))}, + {OFFSET(gpmc_ad13), (MODE(1))}, + {OFFSET(gpmc_ad14), (MODE(1))}, + {OFFSET(gpmc_ad15), (MODE(1))}, + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_vsync), (MODE(0))}, + {OFFSET(lcd_hsync), (MODE(0))}, + {OFFSET(lcd_pclk), (MODE(0))}, + {OFFSET(lcd_ac_bias_en), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii_pin_mux[] = { + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, + {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_fsr), (MODE(7))}, + {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)}, + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux usb1_pin_mux[] = { + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux spi1_pin_mux[] = { + {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux jtag_pin_mux[] = { + {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, + {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux ainx_pin_mux[] = { + {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux rtc_pin_mux[] = { + {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux gpmc_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux pmic_pin_mux[] = { + {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux osc_pin_mux[] = { + {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux pwm_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(gpmc_a2), (MODE(6))}, + {OFFSET(gpmc_a3), (MODE(6))}, + {-1}, +}; + +static struct module_pin_mux emu_pin_mux[] = { + {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux vref_pin_mux[] = { + {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux misc_pin_mux[] = { + {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(ddr_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mii_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(usb1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(jtag_pin_mux); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ainx_pin_mux); + configure_module_pin_mux(rtc_pin_mux); + configure_module_pin_mux(gpmc_pin_mux); + configure_module_pin_mux(pmic_pin_mux); + configure_module_pin_mux(osc_pin_mux); + configure_module_pin_mux(pwm_pin_mux); + configure_module_pin_mux(emu_pin_mux); + configure_module_pin_mux(vref_pin_mux); + configure_module_pin_mux(misc_pin_mux); +} diff --git a/roms/u-boot/board/siemens/smartweb/Kconfig b/roms/u-boot/board/siemens/smartweb/Kconfig new file mode 100644 index 000000000..0871bcc32 --- /dev/null +++ b/roms/u-boot/board/siemens/smartweb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SMARTWEB + +config SYS_BOARD + default "smartweb" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "smartweb" + +endif diff --git a/roms/u-boot/board/siemens/smartweb/MAINTAINERS b/roms/u-boot/board/siemens/smartweb/MAINTAINERS new file mode 100644 index 000000000..51298ffb5 --- /dev/null +++ b/roms/u-boot/board/siemens/smartweb/MAINTAINERS @@ -0,0 +1,6 @@ +SMARTWEB_HW BOARD +M: Heiko Schocher <hs@denx.de> +S: Maintained +F: board/siemens/smartweb +F: include/configs/smartweb.h +F: configs/smartweb_defconfig diff --git a/roms/u-boot/board/siemens/smartweb/Makefile b/roms/u-boot/board/siemens/smartweb/Makefile new file mode 100644 index 000000000..49cb32491 --- /dev/null +++ b/roms/u-boot/board/siemens/smartweb/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2012 +# Markus Hubig <mhubig@imko.de> +# IMKO GmbH <www.imko.de> +# +# (C) Copyright 2014 +# Heiko Schocher <hs@denx.de> +# DENX Software Engineering GmbH + +obj-y += smartweb.o diff --git a/roms/u-boot/board/siemens/smartweb/smartweb.c b/roms/u-boot/board/siemens/smartweb/smartweb.c new file mode 100644 index 000000000..d500a6214 --- /dev/null +++ b/roms/u-boot/board/siemens/smartweb/smartweb.c @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * Achim Ehrlich <aehrlich@taskit.de> + * taskit GmbH <www.taskit.de> + * + * (C) Copyright 2012- + * Markus Hubig <mhubig@imko.de> + * IMKO GmbH <www.imko.de> + * (C) Copyright 2014 + * Heiko Schocher <hs@denx.de> + * DENX Software Engineering GmbH + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <net.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9_sdramc.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_serial.h> +#include <asm/arch/at91_spi.h> +#include <spi.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <watchdog.h> +# include <net.h> +#ifndef CONFIG_DM_ETH +# include <netdev.h> +#endif +#include <g_dnl.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void smartweb_request_gpio(void) +{ + gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(AT91_PIN_PA26, "ena PHY"); +} + +static void smartweb_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +static void smartweb_macb_hw_init(void) +{ + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + + /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ + at91_set_gpio_output(AT91_PIN_PA26, 0); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), + &pioa->pudr); + + at91_phy_reset(); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), + &pioa->puer); + + /* Initialize EMAC=MACB hardware */ + at91_macb_hw_init(); +} + +#ifdef CONFIG_USB_GADGET_AT91 +#include <linux/usb/at91_udc.h> + +void at91_udp_hw_init(void) +{ + /* Enable PLLB */ + at91_pllb_clk_enable(get_pllb_init()); + + /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ + at91_periph_clk_enable(ATMEL_ID_UDP); + + at91_system_clk_enable(AT91SAM926x_PMC_UDP); +} + +struct at91_udc_data board_udc_data = { + .baseaddr = ATMEL_BASE_UDP0, +}; +#endif + +int board_early_init_f(void) +{ + /* enable this here, as we have SPL without serial support */ + at91_seriald_hw_init(); + smartweb_request_gpio(); + return 0; +} + +int board_init(void) +{ + smartweb_request_gpio(); + /* power LED red */ + at91_set_gpio_output(AT91_PIN_PC6, 0); + at91_set_gpio_output(AT91_PIN_PC7, 1); + /* alarm LED off */ + at91_set_gpio_output(AT91_PIN_PC8, 0); + at91_set_gpio_output(AT91_PIN_PC9, 0); + /* prog LED red */ + at91_set_gpio_output(AT91_PIN_PC10, 0); + at91_set_gpio_output(AT91_PIN_PC11, 1); + +#ifdef CONFIG_USB_GADGET_AT91 + at91_udp_hw_init(); + at91_udc_probe(&board_udc_data); +#endif + + /* Adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + smartweb_nand_hw_init(); + smartweb_macb_hw_init(); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifndef CONFIG_DM_ETH +#ifdef CONFIG_MACB +int board_eth_init(struct bd_info *bis) +{ + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); +} +#endif /* CONFIG_MACB */ +#endif + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> +#include <spi_flash.h> + +void matrix_init(void) +{ + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + + writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) + | AT91_MATRIX_SLOT_CYCLE_(0x40), + &mat->scfg[3]); +} + +void at91_spl_board_init(void) +{ + smartweb_request_gpio(); + /* power LED orange */ + at91_set_gpio_output(AT91_PIN_PC6, 1); + at91_set_gpio_output(AT91_PIN_PC7, 1); + /* alarm LED orange */ + at91_set_gpio_output(AT91_PIN_PC8, 1); + at91_set_gpio_output(AT91_PIN_PC9, 1); + /* prog LED red */ + at91_set_gpio_output(AT91_PIN_PC10, 0); + at91_set_gpio_output(AT91_PIN_PC11, 1); + + smartweb_nand_hw_init(); + at91_set_gpio_input(AT91_PIN_PA28, 1); + at91_set_gpio_input(AT91_PIN_PA29, 1); + + /* check if both button are pressed */ + if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && + at91_get_gpio_value(AT91_PIN_PA29) == 0) { + smartweb_nand_hw_init(); + nand_init(); + spl_nand_erase_one(0, 0); + } +} + +#define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \ + | AT91_SDRAMC_CAS_2 \ + | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ + | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \ + | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \ + | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8)) + +void mem_init(void) +{ + struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC; + struct sdramc_reg setting; + + setting.cr = SDRAM_BASE_CONF; + setting.mdr = AT91_SDRAMC_MD_SDRAM; + setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + + /* + * I write here directly in this register, because this + * approach is smaller than calling at91_set_a_periph() in a + * for loop. This saved me 96 bytes. + */ + writel(0xffff0000, &port->pdr); + + writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa); + sdramc_initialize(ATMEL_BASE_CS1, &setting); +} +#endif + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + g_dnl_set_serialnumber("1"); + return 0; +} diff --git a/roms/u-boot/board/siemens/taurus/Kconfig b/roms/u-boot/board/siemens/taurus/Kconfig new file mode 100644 index 000000000..28816bc1a --- /dev/null +++ b/roms/u-boot/board/siemens/taurus/Kconfig @@ -0,0 +1,28 @@ +if TARGET_TAURUS + +config SYS_BOARD + default "taurus" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "taurus" + +choice + prompt "Board Type AXM/TAURUS" + default BOARD_AXM + +config BOARD_AXM + bool "AXM board type" + help + Select this, if you want to build for AXM board. + +config BOARD_TAURUS + bool "TAURUS board type" + help + Select this, if you want to build for TAURUS board. + +endchoice + +endif diff --git a/roms/u-boot/board/siemens/taurus/MAINTAINERS b/roms/u-boot/board/siemens/taurus/MAINTAINERS new file mode 100644 index 000000000..74e3518e0 --- /dev/null +++ b/roms/u-boot/board/siemens/taurus/MAINTAINERS @@ -0,0 +1,7 @@ +TAURUS BOARD +M: Heiko Schocher <hs@denx.de> +S: Maintained +F: board/siemens/taurus/ +F: include/configs/taurus.h +F: configs/axm_defconfig +F: configs/taurus_defconfig diff --git a/roms/u-boot/board/siemens/taurus/Makefile b/roms/u-boot/board/siemens/taurus/Makefile new file mode 100644 index 000000000..8c3b1c1c6 --- /dev/null +++ b/roms/u-boot/board/siemens/taurus/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile for Siemens TAURUS (AT91SAM9G20) based board +# (C) Copyright 2013 Siemens AG +# +# Based on: +# U-Boot file: board/atmel/at91sam9260ek/Makefile +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> + +obj-y += taurus.o diff --git a/roms/u-boot/board/siemens/taurus/taurus.c b/roms/u-boot/board/siemens/taurus/taurus.c new file mode 100644 index 000000000..cad16f906 --- /dev/null +++ b/roms/u-boot/board/siemens/taurus/taurus.c @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for Siemens TAURUS (AT91SAM9G20) based boards + * (C) Copyright Siemens AG + * + * Based on: + * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c + * + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#include <command.h> +#include <common.h> +#include <dm.h> +#include <env.h> +#include <flash.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91sam9_sdramc.h> +#include <asm/arch/atmel_serial.h> +#include <asm/arch/clk.h> +#include <asm/gpio.h> +#include <linux/mtd/rawnand.h> +#include <atmel_mci.h> +#include <asm/arch/at91_spi.h> +#include <spi.h> + +#include <net.h> +#ifndef CONFIG_DM_ETH +#include <netdev.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void taurus_request_gpio(void) +{ + gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(AT91_PIN_PA25, "ena PHY"); +} + +static void taurus_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> +#include <spi_flash.h> + +void matrix_init(void) +{ + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + + writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) + | AT91_MATRIX_SLOT_CYCLE_(0x40), + &mat->scfg[3]); +} + +#if defined(CONFIG_BOARD_AXM) +static int at91_is_recovery(void) +{ + if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) && + (at91_get_gpio_value(AT91_PIN_PA27) == 0)) + return 1; + + return 0; +} +#elif defined(CONFIG_BOARD_TAURUS) +static int at91_is_recovery(void) +{ + if (at91_get_gpio_value(AT91_PIN_PA31) == 0) + return 1; + + return 0; +} +#endif + +void spl_board_init(void) +{ + taurus_nand_hw_init(); + at91_spi0_hw_init(TAURUS_SPI_MASK); + +#if defined(CONFIG_BOARD_AXM) + /* Configure LED PINs */ + at91_set_gpio_output(AT91_PIN_PA6, 0); + at91_set_gpio_output(AT91_PIN_PA8, 0); + at91_set_gpio_output(AT91_PIN_PA9, 0); + at91_set_gpio_output(AT91_PIN_PA10, 0); + at91_set_gpio_output(AT91_PIN_PA11, 0); + at91_set_gpio_output(AT91_PIN_PA12, 0); + + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PA26, 1); + at91_set_gpio_input(AT91_PIN_PA27, 1); +#elif defined(CONFIG_BOARD_TAURUS) + at91_set_gpio_input(AT91_PIN_PA31, 1); +#endif + + /* check for recovery mode */ + if (at91_is_recovery() == 1) { + struct spi_flash *flash; + + puts("Recovery button pressed\n"); + nand_init(); + spl_nand_erase_one(0, 0); + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + 0, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!flash) { + puts("no flash\n"); + } else { + puts("erase spi flash sector 0\n"); + spi_flash_erase(flash, 0, + CONFIG_SYS_NAND_U_BOOT_SIZE); + } + } +} + +#define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \ + |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ + | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \ + | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \ + | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10)) + +void sdramc_configure(unsigned int mask) +{ + struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct sdramc_reg setting; + + at91_sdram_hw_init(); + setting.cr = SDRAM_BASE_CONF | mask; + setting.mdr = AT91_SDRAMC_MD_SDRAM; + setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + + writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | + AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, + &ma->ebicsa); + + sdramc_initialize(ATMEL_BASE_CS1, &setting); +} + +void mem_init(void) +{ + unsigned int ram_size = 0; + + /* Configure SDRAM for 128MB */ + sdramc_configure(AT91_SDRAMC_NC_10); + + /* Do memtest for 128MB */ + ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + /* + * If 32MB or 16MB should be supported check also for + * expected mirroring at A16 and A17 + * To find mirror addresses depends how the collumns are connected + * at RAM (internaly or externaly) + * If the collumns are not in inverted order the mirror size effect + * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal + */ + + /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ + if (ram_size == 0x800) { + printf("\n\r 64MB\n"); + sdramc_configure(AT91_SDRAMC_NC_9); + } else { + /* Size already initialized */ + printf("\n\r 128MB\n"); + } +} +#endif + +#ifdef CONFIG_MACB +static void siemens_phy_reset(void) +{ + /* + * we need to reset PHY for 200us + * because of bug in ATMEL G20 CPU (undefined initial state of GPIO) + */ + if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) == + AT91_RSTC_RSTTYP_GENERAL) + at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */ +} + +static void taurus_macb_hw_init(void) +{ + /* Enable EMAC clock */ + at91_periph_clk_enable(ATMEL_ID_EMAC0); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0); + + siemens_phy_reset(); + + at91_phy_reset(); + + at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */ + + /* Re-enable pull-up */ + at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1); + + /* Initialize EMAC=MACB hardware */ + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(struct bd_info *bd) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI); +} +#endif + +int board_early_init_f(void) +{ + /* Enable clocks for all PIOs */ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + + at91_seriald_hw_init(); + taurus_request_gpio(); + + return 0; +} + +#ifdef CONFIG_USB_GADGET_AT91 +#include <linux/usb/at91_udc.h> + +void at91_udp_hw_init(void) +{ + /* Enable PLLB */ + at91_pllb_clk_enable(get_pllb_init()); + + /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ + at91_periph_clk_enable(ATMEL_ID_UDP); + + at91_system_clk_enable(AT91SAM926x_PMC_UDP); +} + +struct at91_udc_data board_udc_data = { + .baseaddr = ATMEL_BASE_UDP0, +}; +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + taurus_request_gpio(); +#ifdef CONFIG_CMD_NAND + taurus_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + taurus_macb_hw_init(); +#endif + at91_spi0_hw_init(TAURUS_SPI_MASK); +#ifdef CONFIG_USB_GADGET_AT91 + at91_udp_hw_init(); + at91_udc_probe(&board_udc_data); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#if !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_BOARD_AXM) +/* + * Booting the Fallback Image. + * + * The function is used to provide and + * boot the image with the fallback + * parameters, incase if the faulty image + * in upgraded over the base firmware. + * + */ +static int upgrade_failure_fallback(void) +{ + char *partitionset_active = NULL; + char *rootfs = NULL; + char *rootfs_fallback = NULL; + char *kern_off; + char *kern_off_fb; + char *kern_size; + char *kern_size_fb; + + partitionset_active = env_get("partitionset_active"); + if (partitionset_active) { + if (partitionset_active[0] == 'A') + env_set("partitionset_active", "B"); + else + env_set("partitionset_active", "A"); + } else { + printf("partitionset_active missing.\n"); + return -ENOENT; + } + + rootfs = env_get("rootfs"); + rootfs_fallback = env_get("rootfs_fallback"); + env_set("rootfs", rootfs_fallback); + env_set("rootfs_fallback", rootfs); + + kern_size = env_get("kernel_size"); + kern_size_fb = env_get("kernel_size_fallback"); + env_set("kernel_size", kern_size_fb); + env_set("kernel_size_fallback", kern_size); + + kern_off = env_get("kernel_Off"); + kern_off_fb = env_get("kernel_Off_fallback"); + env_set("kernel_Off", kern_off_fb); + env_set("kernel_Off_fallback", kern_off); + + env_set("bootargs", '\0'); + env_set("upgrade_available", '\0'); + env_set("boot_retries", '\0'); + env_save(); + + return 0; +} + +static int do_upgrade_available(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + unsigned long upgrade_available = 0; + unsigned long boot_retry = 0; + char boot_buf[10]; + + upgrade_available = simple_strtoul(env_get("upgrade_available"), NULL, + 10); + if (upgrade_available) { + boot_retry = simple_strtoul(env_get("boot_retries"), NULL, 10); + boot_retry++; + sprintf(boot_buf, "%lx", boot_retry); + env_set("boot_retries", boot_buf); + env_save(); + + /* + * Here the boot_retries count is checked, and if the + * count becomes greater than 2 switch back to the + * fallback, and reset the board. + */ + + if (boot_retry > 2) { + if (upgrade_failure_fallback() == 0) + do_reset(NULL, 0, 0, NULL); + return -1; + } + } + return 0; +} + +U_BOOT_CMD( + upgrade_available, 1, 1, do_upgrade_available, + "check Siemens update", + "no parameters" +); +#endif +#endif |