diff options
Diffstat (limited to 'roms/u-boot/board/spear/x600')
| -rw-r--r-- | roms/u-boot/board/spear/x600/Kconfig | 18 | ||||
| -rw-r--r-- | roms/u-boot/board/spear/x600/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/spear/x600/Makefile | 11 | ||||
| -rw-r--r-- | roms/u-boot/board/spear/x600/fpga.c | 265 | ||||
| -rw-r--r-- | roms/u-boot/board/spear/x600/fpga.h | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/spear/x600/x600.c | 150 |
6 files changed, 456 insertions, 0 deletions
diff --git a/roms/u-boot/board/spear/x600/Kconfig b/roms/u-boot/board/spear/x600/Kconfig new file mode 100644 index 000000000..59f2b1ef5 --- /dev/null +++ b/roms/u-boot/board/spear/x600/Kconfig @@ -0,0 +1,18 @@ +if TARGET_X600 + +config SPL_LDSCRIPT + default "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" + +config SYS_BOARD + default "x600" + +config SYS_VENDOR + default "spear" + +config SYS_SOC + default "spear" + +config SYS_CONFIG_NAME + default "x600" + +endif diff --git a/roms/u-boot/board/spear/x600/MAINTAINERS b/roms/u-boot/board/spear/x600/MAINTAINERS new file mode 100644 index 000000000..bff682494 --- /dev/null +++ b/roms/u-boot/board/spear/x600/MAINTAINERS @@ -0,0 +1,6 @@ +X600 BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/spear/x600/ +F: include/configs/x600.h +F: configs/x600_defconfig diff --git a/roms/u-boot/board/spear/x600/Makefile b/roms/u-boot/board/spear/x600/Makefile new file mode 100644 index 000000000..3ed841577 --- /dev/null +++ b/roms/u-boot/board/spear/x600/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +else +obj-y := fpga.o x600.o +endif diff --git a/roms/u-boot/board/spear/x600/fpga.c b/roms/u-boot/board/spear/x600/fpga.c new file mode 100644 index 000000000..5140694b9 --- /dev/null +++ b/roms/u-boot/board/spear/x600/fpga.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <log.h> +#include <spartan3.h> +#include <command.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_ssp.h> +#include <linux/delay.h> + +/* + * FPGA program pin configuration on X600: + * + * Only PROG and DONE are connected to GPIOs. INIT is not connected to the + * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use + * 16bit serial writes via this SSP port to write the data bits into the + * FPGA. + */ +#define CONFIG_SYS_FPGA_PROG 2 +#define CONFIG_SYS_FPGA_DONE 3 + +/* + * Set the active-low FPGA reset signal. + */ +static void fpga_reset(int assert) +{ + /* + * On x600 we have no means to toggle the FPGA reset signal + */ + debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert); +} + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +static int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert); + + gpio_set_value(CONFIG_SYS_FPGA_PROG, assert); + + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +static int fpga_init_fn(int cookie) +{ + static int state; + + debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state); + + /* + * On x600, the FPGA INIT signal is not connected to the SoC. + * We can't read the INIT status. Let's return the "correct" + * INIT signal state generated via a local state-machine. + */ + if (++state == 1) { + return 1; + } else { + state = 0; + return 0; + } +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +static int fpga_done_fn(int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + + /* + * Wait for Tx-FIFO to become empty before looking for DONE + */ + while (!(readl(&ssp->sspsr) & SSPSR_TFE)) + ; + + if (gpio_get_value(CONFIG_SYS_FPGA_DONE)) + return 1; + else + return 0; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +static int fpga_pre_config_fn(int cookie) +{ + debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); + fpga_reset(true); + + return 0; +} + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +static int fpga_post_config_fn(int cookie) +{ + int rc = 0; + + debug("%s:%d: FPGA post configuration\n", __func__, __LINE__); + + fpga_reset(true); + udelay(100); + fpga_reset(false); + udelay(100); + + return rc; +} + +static int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + /* + * No dedicated clock signal on x600 (data & clock generated) + * in SSP interface. So we don't have to do anything here. + */ + return assert_clk; +} + +static int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + static int count; + static u16 data; + + /* + * First collect 16 bits of data + */ + data = data << 1; + if (assert_write) + data |= 1; + + /* + * If 16 bits are not available, return for more bits + */ + count++; + if (count != 16) + return assert_write; + + count = 0; + + /* + * Wait for Tx-FIFO to become ready + */ + while (!(readl(&ssp->sspsr) & SSPSR_TNF)) + ; + + /* Send 16 bits to FPGA via SSP bus */ + writel(data, &ssp->sspdr); + + return assert_write; +} + +static xilinx_spartan3_slave_serial_fns x600_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_post_config_fn, +}; + +static xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) +}; + +/* + * Initialize the SelectMap interface. We assume that the mode and the + * initial state of all of the port pins have already been set! + */ +static void fpga_serialslave_init(void) +{ + debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__); + fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ +} + +static int expi_setup(int freq) +{ + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + int pll2_m, pll2_n, pll2_p, expi_x, expi_y; + + pll2_m = (freq * 2) / 1000; + pll2_n = 15; + pll2_p = 1; + expi_x = 1; + expi_y = 2; + + /* + * Disable reset, Low compression, Disable retiming, Enable Expi, + * Enable soft reset, DMA, PLL2, Internal + */ + writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST | + EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 | + EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24), + &misc->expi_clk_cfg); + + /* + * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters, + * Enable PLL2, Disable reset + */ + writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq); + writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE | + PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl); + + /* + * Disable soft reset + */ + clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST); + + return 0; +} + +/* + * Initialize the fpga + */ +int x600_init_fpga(void) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Enable SSP2 clock */ + writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB, + &misc->periph1_clken); + + /* Set EXPI clock to 45 MHz */ + expi_setup(45000); + + /* Configure GPIO directions */ + gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0); + gpio_direction_input(CONFIG_SYS_FPGA_DONE); + + writel(SSPCR0_DSS_16BITS, &ssp->sspcr0); + writel(SSPCR1_SSE, &ssp->sspcr1); + + /* + * Set lowest prescale divisor value (CPSDVSR) of 2 for max download + * speed. + * + * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1)) + * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz. + */ + writel(2, &ssp->sspcpsr); + + fpga_init(); + fpga_serialslave_init(); + + debug("%s:%d: Adding fpga 0\n", __func__, __LINE__); + fpga_add(fpga_xilinx, &fpga[0]); + + return 0; +} diff --git a/roms/u-boot/board/spear/x600/fpga.h b/roms/u-boot/board/spear/x600/fpga.h new file mode 100644 index 000000000..f5e6f31a4 --- /dev/null +++ b/roms/u-boot/board/spear/x600/fpga.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + */ + +int x600_init_fpga(void); diff --git a/roms/u-boot/board/spear/x600/x600.c b/roms/u-boot/board/spear/x600/x600.c new file mode 100644 index 000000000..9c30581ec --- /dev/null +++ b/roms/u-boot/board/spear/x600/x600.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <flash.h> +#include <init.h> +#include <micrel.h> +#include <nand.h> +#include <net.h> +#include <netdev.h> +#include <phy.h> +#include <rtc.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <linux/mtd/fsmc_nand.h> +#include "fpga.h" + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +int board_init(void) +{ + /* + * X600 is equipped with an M41T82 RTC. This RTC has the + * HT bit (Halt Update), which needs to be cleared upon + * power-up. Otherwise the RTC is halted. + */ + rtc_reset(); + + return spear_board_init(MACH_TYPE_SPEAR600); +} + +int board_late_init(void) +{ + /* + * Monitor and env protection on by default + */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + + CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* Init FPGA subsystem */ + x600_init_fpga(); + + return 0; +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +void board_nand_init(void) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; + + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) + fsmc_nand_init(nand); +} + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short id1, id2; + + /* check whether KSZ9031 or AR8035 has to be configured */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* PHY configuration for Micrel KSZ9031 */ + printf("PHY KSZ9031 detected - "); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x03FF); + } else { + /* PHY configuration for Vitesse VSC8641 */ + printf("PHY VSC8641 detected - "); + + /* Extended PHY control 1, select GMII */ + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + phy_reset(phydev); + + /* Enable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); + + /* Disable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); + + /* Enable clock output pin */ + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + int ret = 0; + + if (designware_initialize(CONFIG_SPEAR_ETHBASE, + PHY_INTERFACE_MODE_GMII) >= 0) + ret++; + + return ret; +} |